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Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

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Abstract

Monolithic integration of photodetectors, analog-to-digital converters, data storage, and digital processing can improve both the performance and the efficiency of future portable image products. However, digitizing and processing a pixel at the detection site presents the design challenge to deliver a system with the required performance at the lowest cost, not just a system with the highest performance. This paper analyzes the area-time efficiency, the area efficiency, and the energy efficiency of a mixed-signal, SIMD focal plane processing architecture that executes front-end image applications with neighborhood processing. Implementations of the focal plane architecture achieve up to 81x higher area efficiency and up to 11x higher energy efficiency when compared to traditional TI DSP chips. Higher efficiency ratings are required to maintain portability while addressing technology limitations such as interconnect wiring density, heat extraction, and battery life. Systems can be implemented with a less expensive fabrication technology by increasing the number of pixels per processing element (PPE).

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Authors and Affiliations

  1. Portable Image Computation Architectures (PICA) Laboratory, Georgia Institute of Technology, School of Electrical and Computer Engineering, Atlanta, GA, 30332-0250, USA

    William H. Robinson & D. Scott Wills

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  1. William H. Robinson
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  2. D. Scott Wills
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Correspondence to William H. Robinson.

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Currently affiliated with the Department of Electrical Engineering and Computer Science at Vanderbilt University.

William H. Robinson is an Assistant Professor in the Department of Electrical Engineering and Computer Science at Vanderbilt University. He received his B.S. in electrical engineering from Florida Agricultural and Mechanical University in 1996 and his M.S. in electrical engineering from the Georgia Institute of Technology (Georgia Tech) in 1998. He received his Ph.D. in electrical and computer engineering from Georgia Tech in 2003. His research explores the system-level integration of computer architecture to understand the impact of technology on architecture design. Topics of interest include computer architecture design, VLSI design, image processing, and mixed-signal integration with applications to portable imaging devices, integrated sensor technology, and system-on-a-chip multimedia processing. He is a member of the IEEE and participates in the Computer Society, the Education Society, and the Lasers and Electro-Optics Society.

D. Scott Wills is a Professor of Electrical and Computer Engineering at the Georgia Institute of Technology. He received his B.S. in Physics from Georgia Tech in 1983, and his S.M., E.E., and Sc.D. in Electrical Engineering and Computer Science from M.I.T. in 1985, 1987, and 1990, respectively. His research interests include short wire VLSI architectures, high throughput portable processing systems, architectural modeling for gigascale (GSI) technology, and high efficiency image processors. He is a senior member of the IEEE and the Computer Society and he is an associate editor of IEEE Transactions on Computers.

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Robinson, W.H., Wills, D.S. Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture. J VLSI Sign Process Syst Sign Image Video Technol 41, 65–80 (2005). https://doi.org/10.1007/s11265-005-6251-5

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