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Buffer and Register Allocation for Memory Space Optimization

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Abstract

In today’s embedded systems, memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia applications using temporary multi-dimensional arrays that are typically used to store intermediate results during multimedia processing. In this paper, we propose a new technique that optimizes the use of the cache and the registers. It consists in combining buffer and register allocation to reduce the size of the temporary arrays. Firstly we use the concept of live data to replace each array by a buffer of lower size. Then we replace references to these buffers by registers. The buffer allocation step keeps only useful data in memory and the register allocation step allows taking advantage of data reuse in internal loops. Codes considered in this paper are multimedia applications structured as a sequence of loop nests. The experiments are made on Unix environment and on the StepNP simulator (MPSoC platform of STMicroelctronics). They show that our technique yields significant reduction of the number of data cache and TLB misses.

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Authors and Affiliations

  1. Génie Informatique, Ecole Polytechnique de Montréal, C.P. 6079, succ. Centre-ville, Montréal, Canada, QC, H3C 3A7

    Youcef Bouchebaba, Bruno Girodias & Gabriela Nicolescu

  2. ENSMP/CRI, 35 Saint Honoré, 77305, Fontainebleau, France

    Fabien Coelho

  3. Université de Montréal, CP 6128, Succ. Centre-Ville, Montréal, Canada, H3C 357

    El mostapha Aboulhamid

Authors
  1. Youcef Bouchebaba
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  2. Bruno Girodias
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  3. Fabien Coelho
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  4. Gabriela Nicolescu
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  5. El mostapha Aboulhamid
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Correspondence to Youcef Bouchebaba.

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Bouchebaba, Y., Girodias, B., Coelho, F. et al. Buffer and Register Allocation for Memory Space Optimization. J VLSI Sign Process Syst Sign Im 49, 123–138 (2007). https://doi.org/10.1007/s11265-006-0001-1

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  • DOI: https://doi.org/10.1007/s11265-006-0001-1

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