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Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions

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Abstract

In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an asynchronous layered interface performing complex functions is readily achieved without repeating the implementation of the whole bus interface. Simulations are carried out to measure the performance and power consumption of implemented asynchronous on-chip bus with the proposed asynchronous layered interface. Simulation results demonstrate that throughput of the asynchronous on-chip bus with multiple outstanding out-of-order transactions is increased by 30.9%, while power consumption overhead is 16.1% and area overhead is 56.8%, as compared to the asynchronous on-chip bus with a single outstanding transaction.

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References

  1. International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2005.

  2. Po-chih Tseng, Yung-chi Chang, Yu-wen Huang, Hung-chi Fang, Chao-tsung Huang, Liang-gee Chen, “Advances in Hardware Architectures for Image and Video Coding—A Survey,” Proc. IEEE, vol. 93, 2004, pp. 184–197.

    Article  Google Scholar 

  3. T. R. Jacobs, V. A. Chouliaras, and D. J. Mulvaney, “Thread-Parallel MPEG-2, MPEG-4 and H.264 Video Encoders for SoC Multi-processor Architectures,” IEEE Trans. Consum. Electron., vol. 52, 2006, pp. 269–275.

    Article  Google Scholar 

  4. A. Dasu and S. Panchanathan, “Reconfigurable Media Processing,” International Conference on Information Technology: Coding and Computing, 2001, pp. 300–304.

  5. E. Salminen, V. Lahtinen, K. Kuusilinna, and T. Hamalainen, “Overview of Bus-Based System-on-Chip Interconnections,” IEEE Int. Symp. Circuits Syst., vol. 2, 2002, pp. 372–375.

    Google Scholar 

  6. D. Flynn, “AMBA: Enabling Reusable On-Chip Designs,” IEEE Micro, vol. 17, 1997, pp. 20–27.

    Article  Google Scholar 

  7. A. Rincon, G. Cherichetti, J. Monzel, D. Stauffer, and M. Trick, “Core Design and System-on-a-Chip Integration,” IEEE Des. Test Comput., vol. 14, 1997, pp. 26–35.

    Article  Google Scholar 

  8. AMBA AXI Protocol Specification, ARM, 2003.

  9. M. Pedram, “Power Minimization in IC Design: Principles and Applications,” ACM Transactions on Design Automation, vol. 1, 1996, pp. 3–56.

    Article  Google Scholar 

  10. R. Sridhar, “Clocking and Synchronization in Sub-90 nm System-on-chip (SoC) Designs,” IEEE Design, Automation and Test in Europe Conference and Exhibition, 2004, pp. 49–84.

  11. D. Chapiro, “Globally-Asynchronous Locally-Synchronous Systems,” Ph.D. dissertation, Stanford Univ., USA, Oct. 1984.

  12. W. J. Bainbridge, “Asynchronous System-on-chip Interconnect,” Ph.D. dissertation, Univ. of Manchester, UK, Mar. 2000.

  13. J. Kessels, A. Peeters, T. Kramer, M. Feuser, and K. Ully, “Designing an Asynchronous Bus Interface,” IEEE International Symposium on Asynchronous Circuits and Systems, Mar. 2001, pp. 108–117.

  14. A. Radulescu, J. Dielissen, S. G. Pestana, O. P. Gangwal, E. Rijpkema, P. Wielage, and K. Goossens, “An Efficient on-Chip NI Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, 2005, pp. 4–17.

    Article  Google Scholar 

  15. J. Sparso and S. Furber, Principles of Asynchronous Circuit Design—A Systems Perspectives, Kluwer, 2002.

  16. L. Zhou and Xiao Yan, “Integration Flow of Video Processing Unit into SoC,” Freescale Semiconductor, 2006.

  17. D. Pajak, “System Solutions for a Baseband SoC,” white paper, ARM, 2006.

  18. C. Evrard, “ARM MPCore—The First Integrated Symmetric Multiprocessor Core,” Sophia Antipolis MicroElectronics Forum, 2004.

  19. D. Sima, T. Fountain, and P. Kacsuk, Advanced Computer Architecture, Addison-Wesley, 1997.

  20. E. Kim, J.-G. Lee, and D.-I. Lee, “Automatic Process-oriented Control Circuit Generation for Asynchronous High-level Synthesis,” IEEE International Symposium on Asynchronous Circuits and Systems, 2000, pp. 104–105.

  21. M. Theobald and S. Nowick, “Transformations for the Synthesis and Optimization of Asynchronous Distributed Control,” IEEE Design Automation Conference, 2001, pp. 263–268.

  22. H. Zimmermann, “OSI Reference Model—the ISO Model of Architecture for Open Systems Interconnection,” IEEE Trans. Commun., vol. 28, 1980, pp. 425–432.

    Article  Google Scholar 

  23. M. Josephs and J. Yantchev, “CMOS Design of the Tree Arbiter Element,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 4, 1996, pp. 472–476.

    Article  Google Scholar 

  24. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, “Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers,” IEICE Trans. Inf. Syst., vol. E-80D, 1997, pp. 315–325.

    Google Scholar 

  25. D. Gilbert, “Dependency and Exception Handling in an Asynchronous Microprocessor,” Ph.D. dissertation, Univ. of Manchester, UK, Mar. 1997.

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Correspondence to Dongsoo Har.

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Jung, EG., Lee, JG., Jhang, KS. et al. Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions. J VLSI Sign Process Syst Sign Image Video Technol 46, 133–151 (2007). https://doi.org/10.1007/s11265-006-0019-4

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  • DOI: https://doi.org/10.1007/s11265-006-0019-4

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