Abstract
This paper presents a new architecture for implementing a two-dimensional Discrete Wavelet Transform (2-D DWT). This architecture works in a non-separable fashion using a parallel filter structure with distributed control to compute all the DWT resolution levels. The architecture is modular and scalable in its totality. In this way, the input sample can be processed at the rate of one sample per clock cycle. To compute an N × N still image with a filter length L, N2 + N clock cycles and 4.5N memory storage cells are required. Implementation results based on a Xilinx Virtex FPGA device are included.
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Ricardo José Colom Palero was born in Cullera, Spain. He received the M.Sc. and Ph.D. degrees from the Polytechnic University of Valencia, Spain, in 1993 and 2001, respectively. Since 1993 he has been a lecturer of the Department of Electronic Engineering at the Polytechnic University of Valencia. Currently, he is Assistant Professor at Telecommunications Engineering School of the Polytechnic University of Valencia, Spain. His areas of research interest include VLSI signal processing, design of FPGA-based systems and custom digital signal processing for audio and video applications.
Rafael Gadea Gironés received the M.Sc. and Ph.D. degrees from the Polytechnic University of Valencia, Spain, in 1990 and 2000, respectively. Since 1992 he has been a lecturer of the Department of Electronic Engineering at the Polytechnic University of Valencia. Currently, he is assistant professor at Telecommunications Engineering School of the Polytechnic University of Valencia, Spain. His areas of research interest include hardware description languages, design of FPGA-based systems and design of neural networks and cellular automatas.
Angel Sebastia Cortes received his MSc degree in Electronic Engineering from the Polytechnic University of Valencia, Spain, in 1985, and his PhD degree in Electronic Engineering from the University of Valencia, in 1991. He is currently a professor at the Department of Electronic Engineering at the Polytechnic University of Valencia. His research interests are high speed data acquisition systems, electronics in nuclear instrumentation and FPGA-based system design.
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Palero, R.J.C., Gironés, R.G. & Cortes, A.S. A Novel FPGA Architecture of a 2-D Wavelet Transform. J VLSI Sign Process Syst Sign Image Video Technol 42, 273–284 (2006). https://doi.org/10.1007/s11265-006-4188-y
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DOI: https://doi.org/10.1007/s11265-006-4188-y