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The Negative Two’s Complement Number System

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Abstract

The two’s complement fractional fixed-point number system is widely used to implement digital signal processing on VLSI chips. It has a range of values from −1 to one least significant bit below +1. Either the multiplication of −1 • −1 or taking the absolute value of −1 produces a result (+1) that cannot be represented. A new system, the negative two’s complement number system, is described here that has a range of one least significant bit above −1 to +1 which eliminates the problem. This paper presents the new number system and describes algorithms for the basic arithmetic operations.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, 78712, USA

    Earl E. Swartzlander Jr.

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  1. Earl E. Swartzlander Jr.
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Correspondence to Earl E. Swartzlander Jr..

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Swartzlander, E.E. The Negative Two’s Complement Number System. J VLSI Sign Process Syst Sign Im 49, 177–183 (2007). https://doi.org/10.1007/s11265-007-0052-y

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  • DOI: https://doi.org/10.1007/s11265-007-0052-y

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