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High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems

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Abstract

We describe an efficient, fully-parallel Network of Programmable Logic Array (NPLA)-based realization of iterative decoders for structured LDPC codes. The LDPC codes are developed in tandem with the underlying VLSI implementation technique, without compromising chip design constraints. Two classes of codes are considered: one, based on combinatorial objects derived from difference sets and generalizations of non-averaging sequences, and another, based on progressive edge-growth techniques. The proposed implementation reduces routing congestion, a major issue not addressed in prior work. The operating power, delay and chip-size of the circuits are estimated, indicating that the proposed method significantly outperforms presently used standard-cell based architectures. The described LDPC designs can be modified to accommodate widely different requirements, such as those arising in recording systems, as well as wireless and optical data transmission devices.

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Authors and Affiliations

  1. University of Colorado, Boulder, CO, USA

    Vijay Nagarajan, Stefan Laendner & Olgica Milenkovic

  2. Texas A&M University, College Station, TX, USA

    Nikhil Jayakumar & Sunil P. Khatri

Authors
  1. Vijay Nagarajan
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  2. Stefan Laendner
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  3. Nikhil Jayakumar
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  4. Olgica Milenkovic
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  5. Sunil P. Khatri
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Corresponding author

Correspondence to Stefan Laendner.

Additional information

Part of this work was presented at Globecom 2004, Dallas, Texas. This work is supported in part by a fellowship from the Institute for Information Transmission, University of Erlangen-Nuremberg, Germany, awarded to Stefan Laendner.

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Nagarajan, V., Laendner, S., Jayakumar, N. et al. High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. J VLSI Sign Process Syst Sign Im 49, 185–206 (2007). https://doi.org/10.1007/s11265-007-0054-9

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  • DOI: https://doi.org/10.1007/s11265-007-0054-9

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