Abstract
Dynamically reconfigurable hardware has already been deployed for accelerating computationally demanding applications. Some of these hardware architectures allow run time reconfiguration but this usually leads to a large reconfiguration overhead. The advantage of run time reconfiguration is that it allows new algorithmic solutions for many applications. To study the potential of frequent run time reconfiguration it is interesting to investigate its costs and benefits from an abstract point of view and to develop new architectural concepts. Multi-level reconfigurable architectures are one such concept that introduces several levels of reconfiguration. This paper deals with new types of multi-level reconfigurable architectures. The corresponding problem of finding the best granularity for different reconfiguration levels is formulated and investigated. Although this problem is shown to be NP-complete, an interesting restricted subcase is solved optimally in polynomial time. For the general case, a good heuristic is proposed that is based on solutions for the restricted case. Results on three example applications show that the reconfiguration cost can be reduced with the new architectures. Based on a proposed measure of relative efficiency it is also shown that the new architectures are more efficient so that they obtain a larger reconfiguration cost reduction with less additional hardware.
Similar content being viewed by others
References
A. Dandalis and V. K. Prasanna, “Configuration Compression for FPGA-Based Embedded Systems,” in ACM Symposium on Field-Programmable Gate Arrays, 2001, pp. 171–210.
S. Hauck, Z. Li, and E. Schwabe, “Configuration Compression for the Xilinx XC6200 FPGA,” IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 18, no. 8, 1999, pp. 1107–1113.
J. Teich and M. Köster, “(Self-)Reconfigurable Finite State Machines: Theory and Implementation,” in DATE ‘02: Proceedings of the Conference on Design, Automation and Test in Europe,” IEEE Computer Society, Washington, DC, USA, 2002, p. 559.
R. P. S. Sidhu, S. Wadhwa, A. Mei, and V. K. Prasanna, “A Self-Reconfigurable Gate Array Architecture,” in FPL ‘00: Proceedings of The Roadmap to Reconfigurable Computing,” 10th International Workshop on Field-Programmable Logic and Applications, Springer, London, UK, 2000, pp. 106–120.
S. Wadhwa, and A. Dandalis, “Efficient Self-reconfigurable Implementations Using on-chip Memory,” in FPL ‘00: Proceedings of The Roadmap to Reconfigurable Computing,” 10th International Workshop on Field-Programmable Logic and Applications, Springer, London, UK, 2000, pp. 443–448.
K. Lee, and D. Wong, “Incremental Reconfiguration of Multi-FPGA Systems,” in ACM Symposium on Field Programmable Gate Arrays, 2002, pp. 206–213.
S. Lange, and M. Middendorf, “Hyperreconfigurable Architectures and the Partition into Hypercontexts Problem,” Journal of Parallel and Distributed Computing, vol. 65, no. 6, 2005, pp. 743–754.
S. Lange, and M. Middendorf, “Multi-level Reconfigurable Architectures in the Switch Model,” in Proc. Reconfigurable Architectures Workshop (RAW 2006), 2006, p. 8.
S. Lange, and M. Middendorf, “Granularity Aspects for the Design of Multi-level Reconfigurable Architectures,” in IEEE International Conference on Field-Programmable Technology (FPT 2006), 2006, pp. 9–16.
S. Shukla, N. W. Bergmann, and J. Becker, “Quku: A Two-level Reconfigurable Architecture,” in IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI), 2006, pp. 109–116.
E. Mirsky, A. DeHon, “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources,” in IEEE Symposium on FPGAs for Custom Computing Machines, K. L. Pocek, J. Arnold (Eds.), IEEE Computer Society Press, Los Alamitos, CA, 1996, pp. 157–166.
S. Lange, M. Middendorf, “On the Design of Two-level Reconfigurable Architectures,” in International Conference on Reconfigurable Computing and FPGAs (ReConFig 05), Puebla, Mexico, 2005, p. 8.
A. DeHon, “Entropy, Counting, and Programmable Interconnect,” in FPGA ‘96: Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays, ACM, New York, NY, USA, 1996, pp. 73-79.
M. R. Garey and D. S. Johnson, “Computers and Intractability: A Guide to the Theory of NP-Completeness,” Freeman, 1979.
J. Tan and L. Zhang, “The Consecutive Ones Submatrix Problem for Sparse Matrices,” Algorithmica, vol. 48, no. 3, 2007, pp. 287–299.
J. E. Atkins, E. G. Boman, and B. Hendrickson, “A Spectral Algorithm for Seriation and the Consecutive Ones Problem,” SIAM J. Comput., vol. 28, no. 1, 1999, pp. 297–310.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Lange, S., Middendorf, M. Design Aspects of Multi-level Reconfigurable Architectures. J Sign Process Syst Sign Image 51, 23–37 (2008). https://doi.org/10.1007/s11265-007-0134-x
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-007-0134-x