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Parallel Memory Architecture for Elliptic Curve Cryptography over \( \mathbb{G}\mathbb{F}{\left( p \right)} \) Aimed at Efficient FPGA Implementation

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Abstract

Parallelization of operations is of utmost importance for efficient implementation of Public Key Cryptography algorithms. Starting with a classification of parallelization methods at different abstraction levels of public key algorithms, we propose a novel memory architecture for elliptic curve implementations with multiple modular multiplier units. This architecture is well-suited for different point addition and doubling algorithms over \( \mathbb{G}\mathbb{F}{\left( p \right)} \) to be implemented on FPGAs. It allows the execution time to scale with the number of modular multipliers and exhibits nearly no overhead compared to the mere runtime of the multipliers. The advantages of this distributed memory architecture are demonstrated by means of two different point addition and doubling algorithms.

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References

  1. Siddika Berna Örs, Lejla Batina, Bart Preneel, and Joos Vandewalle, “Hardware Implementation of a Montgomery Modular Multiplier in a Systolic Array,” International Parallel and Distributed Processing Symposium—IPDPS, 2003, pp. 184–191.

  2. Siddika Berna Örs, Lejla Batina, Bart Preneel, and Joos Vandewalle, “Hardware Implementation of an Elliptic Curve Processor over \( \mathbb{G}\mathbb{F}{\left( p \right)} \), IEEE International,” Conference on Application-Specific Systems, Architectures, and Processors—ASAP, 2003, pp. 24–26.

  3. Francis Crowe, Alan Daly, and William P. Marnane, “A Scalable Dual Mode Arithmetic Unit for Public Key Cryptosystems,” International Conference on Information Technology: Coding and Computing—ITCC, Volume 1, 2005, pp. 568–573.

  4. Colin D. Walter, “Systolic Modular Multiplication,” IEEE Trans. Comput., vol. 42, no. 3, 1993, pp. 376–378.

    Article  Google Scholar 

  5. Alexandre F. Tenca and Ç.K. Koç, “A Scalable Architecture for Modular Multiplication Based on Montgomery’s Algorithm,” IEEE Trans. Comput., vol. 52, no. 9, 2003, pp. 1215–1221.

    Article  Google Scholar 

  6. Nazar A. Saqib, Francisco Rodríguez-Henríquez, and Arturo Díaz-Pérez, “A Parallel Architecture for Computing Scalar Multiplication on Hessian Elliptic Curves,” International Conference on Information Technology: Coding and Computing—ITCC, Volume 2, 2003, pp. 493–497.

  7. Rainer Blümel, Ralf Laue, and Sorin A. Huss, “A Highly Efficient Modular Multiplication Algorithm for Finite Field Arithmetic in \( \mathbb{G}\mathbb{F}{\left( p \right)} \),” ECRYPT Workshop: CRyptographic Advances in Secure Hardware–CRASH, 2005.

  8. Markus Ernst, Michael Jung, Felix Madlener, Sorin A. Huss, and Rainer Blümel, “A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over \( \mathbb{G}\mathbb{F}{\left( {2^{m} } \right)} \),” Workshop on Cryptographic Hardware and Embedded Systems—CHES, ser. Lect. Notes Comput. Sci., vol. 2523, 2002, pp. 381–399.

    Google Scholar 

  9. Jean-Claude Bajard and Laurent Imbert, “A Full RNS Implementation of RSA,” IEEE Trans. Comput., vol. 53, no. 6, 2004, pp. 769–774.

    Article  Google Scholar 

  10. Mathieu Ciet, Michael Neve, Eric Peeters, and Jean-Jacques Quisquater, “Parallel FPGA Implementation of RSA with Residue Number Systems—Can side-channel threats be avoided?,” IEEE Midwest International Symposium on Circuits and Systems—MWSCAS, vol. 2, 2003, pp. 806–810.

  11. Dimitris Schinianakis, A.P. Fournaris, Athanasios P. Kakarountas, T. Stouraitis, “An RNS Architecture of an \(F_{p} \) Elliptic Curve Point Multiplier,” IEEE Int. Symp. Circuits Syst.—ISCAS, 2006, pp. 3369–3373.

  12. Kazumaro Aoki, Fumitaka Hoshino, Tetsutaro Kobayashi, and Hiroaki Oguro, “Elliptic Curve Arithmetic Using SIMD,” International Conference on Information Security—ISC, ser. Lect. Notes Comput. Sci., vol. 2200, 2001, pp. 235–247.

    Google Scholar 

  13. Marcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, and Jürgen Teich, “Reconfigurable Implementation of Elliptic Curve Crypto Algorithms,” International Parallel and Distributed Processing Symposium—IPDPS, 2002, pp. 157–164.

  14. Guido Bertoni, Luca Breveglieri, Thomas J. Wollinger, and Christof Paar, “Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems,” International Conference on Information Technology: Coding and Computing—ITCC, 2004, pp. 538–544.

  15. Tetsuya Izu and Tsuyoshi Takagi, “A Fast Parallel Elliptic Curve Multiplication Resistant against Side Channel Attacks, ” International Workshop on Practice and Theory in Public Key Cryptosystems: Public Key Cryptography, ser. Lect. Notes Comput. Sci. vol. 2274, 2002, pp. 280–296.

    Google Scholar 

  16. Tetsuya Izu and Tsuyoshi Takagi, “Fast Elliptic Curve Multiplications with SIMD Operations,” International Conference on Information and Communications Security—ICICS, ser. Lect. Notes Comput. Sci., vol. 2513, 2002, pp. 217–230.

    Google Scholar 

  17. Marc Joye and Sung-Ming Yen, “The Montgomery Powering Ladder,” Workshop on Cryptographic Hardware and Embedded Systems—CHES, ser. Lect. Notes Comput. Sci., vol. 2523, 2002, pp. 291–302.

    Google Scholar 

  18. Pradeep Kumar Mishra, “Pipelined Computation of Scalar Multiplication in Elliptic Curve Cryptosystems,” Workshop on Cryptographic Hardware and Embedded Systems—CHES, ser. Lect. Notes Comput. Sci., vol. 3156, 2004, pp. 328–342.

    Article  Google Scholar 

  19. Nadia Nedjah and Luiza de Macedo Mourelle, “Reconfigurable Hardware Implementation of Montgomery Modular Multiplication and Parallel Binary Exponentiation,” Euromicro Symposium on Digital Systems Design—DSD, 2002, pp. 226–235.

  20. Wieland Fischer, Christophe Giraud, and Erik Woodward Knudsen, “Parallel Scalar Multiplication on General Elliptic Curves Over \(F_{p} \) hedged against Non-Differential Side-Channel Attacks,” Cryptology ePrint Archive, Report 2002/007, IACR, 2002.

  21. IEEE 1363, “Standard Specifications for Public-Key Cryptography—Annex A,” http://grouper.ieee.org/groups/1363/, 2000.

  22. XILINX, “Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheets,” http://www.xilinx.com/products/, 2005.

  23. Nick Sawyer and Marc Defossez, “Quad-Port Memories in Virtex Devices, XILINX,” http://direct.xilinx.com/bvdocs/appnotes/xapp228.pdf, 2002.

  24. Atmel, “AT40K05/10/20/40AL Summary,” http://www.atmel.com/dyn/resources/prod_documents/2818s.pdf, 2004.

  25. QuickLogic, “Eclipse Family Data Sheet (Rev. D),” http://www.quicklogic.com/images/Eclipse_Family_DS.pdf, 2005.

  26. Arshad Jhumka, Stephan Klaus, and Sorin A. Huss, “ A Dependability-Driven System-Level Design Approach for Embedded Systems, Design, Automation and Test in Europe—DATE,” 2005, pp. 372–377.

  27. Stephan Klaus, “System-Level Design Methodology for Embedded Systems (in German),” Technische Universtität Darmstadt, Computer Science Department, PhD Thesis, 2005.

  28. Stephan Klaus and Sorin A. Huss, “Konzepte zur Beherrschung der Entwurfskomplexität eingebetteter Systeme (Concepts for the Control of the Complexity of Embedded System Design),” it—Information Technology, Methoden und innovative Anwendungen der Informatik und Informationstechnik, vol. 46, no. 2, 2004, pp. 59–66.

  29. Chae Hoon Lim and Pil Joong Lee, “More Flexible Exponentiation with Precomputation,” Advances in Cryptography—CRYPTO, ser. Lect. Notes Comput. Sci., vol. 839, 1994, pp. 95–107.

    MathSciNet  Google Scholar 

  30. Gerardo Orlando and Christof Paar, “A Scalable \( \mathbb{G}\mathbb{F}{\left( p \right)} \) Elliptic Curve Processor Architecture for Programmable Hardware,” Workshop on Cryptographic Hardware and Embedded Systems—CHES, ser. Lect. Notes Comput. Sci., vol. 2162, 2001, pp. 348–363.

    Article  MathSciNet  Google Scholar 

  31. Francisco Rodríguez-Henríquez and Çetin Kaya Koç, “On Fully Parallel Karatsuba Multipliers for \( \mathbb{G}\mathbb{F}{\left( {2^{m} } \right)} \),” International Conference on Computer Science and Technology—CST, 2003, pp. 405–410.

  32. Nadia Nedjah and Luiza de Macedo Mourelle, “Fast Less Recursive Hardware for Large Number Multiplication Using Karatsuba-Ofman’s Algorithm, ”Comput. Inf. Sci.—ISCIS, 2003, pp. 43–50.

  33. Colin D. Walter, “Improved Linear Systolic Array for Fast Modular Exponentiation,” IEE Proc. Comput. Digit. Tech., vol. 147, no. 5, 2000, pp. 323–328.

    Article  Google Scholar 

  34. Anatolii Karatsuba and Yu Ofman, “Multiplication of Multidigit Numbers on Automata,” Sov. Phys.—Doklady (Engl. transl.), vol. 7, no. 7, 1963, pp. 595–596.

    Google Scholar 

  35. Alfred J. Menezes, Paul C. van Oorschot, and Scott A. Vanstone, “Handbook of Applied Cryptography”, CRC Press, 1997.

  36. Mikaël Després, “Comparison of Optimization Algorithms Aimed to Design Space Exploration of Embedded Systems (in German),” Technische Universität Darmstadt, Computer Science Department, Diploma Thesis, 2006.

  37. Fred Glover and Fred Laguna, “Tabu Search,” Kluwer Academic Publishers, Norwell, MA, USA, 1997.

    MATH  Google Scholar 

  38. Scott Kirkpatrick, D. Gelatt Jr., and Mario P. Vecchi, “Optimization by Simmulated Annealing,” Science, vol. 220, no. 4598, 1983, pp. 671–680.

    Article  MathSciNet  Google Scholar 

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Authors and Affiliations

  1. Integrated Circuits and Systems Laboratory, Department of Computer Science, Technische Universität Darmstadt, Darmstadt, Germany

    Ralf Laue & Sorin A. Huss

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  1. Ralf Laue
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  2. Sorin A. Huss
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Correspondence to Ralf Laue.

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This work was supported by the research program SicAri of BMBF (German Federal Ministry of Education and Research)

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Laue, R., Huss, S.A. Parallel Memory Architecture for Elliptic Curve Cryptography over \( \mathbb{G}\mathbb{F}{\left( p \right)} \) Aimed at Efficient FPGA Implementation. J Sign Process Syst Sign Image 51, 39–55 (2008). https://doi.org/10.1007/s11265-007-0135-9

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