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Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs

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Abstract

The suitability of the 2D Discrete Wavelet Transform (DWT) as a tool in image and video compression is nowadays indisputable. For the execution of the multilevel 2D DWT, several computation schedules based on different input traversal patterns have been proposed. Among these, the most commonly used in practical designs are: the row–column, the line-based and the block-based. In this work, these schedules are implemented on FPGA-based platforms for the forward 2D DWT by using a lifting-based filter-bank implementation. Our designs were realized in VHDL and optimized in terms of throughput and memory requirements, in accordance with the principles of both the schedules and the lifting decomposition. The implementations are fully parameterized with respect to the size of the input image and the number of decomposition levels. We provide detailed experimental results concerning the throughput, the area, the memory requirements and the energy dissipation, associated with every point of the parameter space. These results demonstrate that the choice of the suitable schedule is a decision that should be dependent on the given algorithmic specifications.

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Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Imperial College London, Exhibition Road, London, SW7 2BT, UK

    Maria E. Angelopoulou & Peter Y. K. Cheung

  2. Department of Computer Science and Technology, University of Peloponnese, Tripolis, 22100, Greece

    Konstantinos Masselos

  3. Department of Electronic Engineering, Queen Mary University of London, Mile End Road, London, E1 4NS, UK

    Yiannis Andreopoulos

Authors
  1. Maria E. Angelopoulou
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  2. Konstantinos Masselos
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  3. Peter Y. K. Cheung
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  4. Yiannis Andreopoulos
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Correspondence to Maria E. Angelopoulou.

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Angelopoulou, M.E., Masselos, K., Cheung, P.Y.K. et al. Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs. J Sign Process Syst Sign Image 51, 3–21 (2008). https://doi.org/10.1007/s11265-007-0139-5

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  • DOI: https://doi.org/10.1007/s11265-007-0139-5

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