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Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box

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Abstract

Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, wherein hardware designs for FPGAs and standard cells received particular attention. In this paper we present a comprehensive study of different standard-cell implementations of the AES S-box with respect to timing (i.e. critical path), silicon area, power consumption, and combinations of these cost metrics. We examine implementations which exploit the mathematical properties of the AES S-box, constructions based on hardware look-up tables, and dedicated low-power solutions. Our results show that the timing, area, and power properties of the different S-box realizations can vary by up to almost an order of magnitude. In terms of area and area-delay product, the best choice are implementations which calculate the S-box output. On the other hand, the hardware look-up solutions are characterized by the shortest critical path. The dedicated low-power implementations do not only reduce power consumption by a large degree, but they also show good timing properties and offer the best power-delay and power-area product, respectively.

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Notes

  1. Unfortunately, the exact performance figures for ROMs were not accessible for the technology we used.

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Acknowledgements

The authors would like to thank Johannes Wolkerstorfer and David Canright for providing the HDL source code of several AES S-box implementations. The research described in this paper has been supported by the Austrian Science Fund (FWF) under grant P16952–N04, the FIT-IT initiative of the Austrian Federal Ministry of Transport, Innovation, and Technology (project SNAP), and the EPSRC under grant EP/E001556/1. The research described in this paper has also been supported, in part, by the European Commission through the IST Programme under contract IST-2002-507932 ECRYPT. The information in this document reflects only the authors’ views, is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability.

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Authors and Affiliations

  1. Institute for Applied Information Processing and Communications, Graz University of Technology, Inffeldgasse 16a, A-8010, Graz, Austria

    Stefan Tillich, Martin Feldhofer & Thomas Popp

  2. Department of Computer Science, University of Bristol, Woodland Road, Bristol, BS8 1UB, UK

    Johann Großschädl

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  1. Stefan Tillich
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  2. Martin Feldhofer
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  3. Thomas Popp
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  4. Johann Großschädl
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Correspondence to Johann Großschädl.

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Tillich, S., Feldhofer, M., Popp, T. et al. Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box. J Sign Process Syst Sign Image 50, 251–261 (2008). https://doi.org/10.1007/s11265-007-0158-2

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  • DOI: https://doi.org/10.1007/s11265-007-0158-2

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