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Pipelined Architecture for Additive Range Reduction

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Abstract

Range reduction is a crucial step for the accuracy in trigonometric functions evaluation. A new pipelined architecture to deal with range reduction for floating point representation is presented in this paper. The algorithm is based on a look-up table storing the corresponding powers of 2 mod A. The overall design has been optimized for a modulo equal to 2π, which is the most widely used due to trigonometric functions requirements. We provide an evaluation of different configurations and a full error propagation study which ensures an accuracy of one unit in the last place.

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Authors and Affiliations

  1. Department of Computers Architecture, University of Málaga, Escuela Técnica Superior de Ingeniería Informática, Campus de Teatinos, Málaga, 29017, Spain

    Francisco J. Jaime, Julio Villalba, Javier Hormigo & Emilio L. Zapata

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  1. Francisco J. Jaime
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  2. Julio Villalba
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  3. Javier Hormigo
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  4. Emilio L. Zapata
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Correspondence to Francisco J. Jaime.

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Jaime, F.J., Villalba, J., Hormigo, J. et al. Pipelined Architecture for Additive Range Reduction. J Sign Process Syst Sign Image Video Technol 53, 103–112 (2008). https://doi.org/10.1007/s11265-008-0166-x

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  • DOI: https://doi.org/10.1007/s11265-008-0166-x

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