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Evaluating SoC Network Performance in MPEG-4 Encoder

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Abstract

This paper shows how a bus topology performs as a System-on-Chip (SoC) interconnection. We measure and analyze Heterogeneous IP Block Interconnection (HIBI) bus for a multiple clock domain, Multiprocessor System-on-Chip (MPSoC) with an MPEG-4 video encoding application on FPGA. The studied MPSoC contains up to 22 IP blocks: 11 soft processors, 8 hardware accelerators and three other components. A novel approach of frequency scaling is used to isolate the impact of various architecture components. The system is benchmarked in various configurations. For example, HIBI is run at 100× speed with respect to processors to resemble ideal interconnection. Based on the measurements with up to 16.9frames/s CIF (352 × 288) encoding speed, estimation for HDTV resolution video encoder is presented. The required optimizations are discussed. Finally, it is shown that 25frames/s 1280 × 720 video encoder needs 55 MHz HIBI but 670 MHz general-purpose soft RISC processors. In practice, the processing performance has to be boosted by implementing hardware acceleration and improving memory hierarchy. Clearly, HIBI is not the limiting factor.

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References

  1. Texas Instruments, “OMAP 3 Family Product Bulletin,” 2007. Available online: http://focus.ti.com/pdfs/wtbu/ti_omap3family.pdf.

  2. Sony, “Cell Broadband Engine Architecture,” Version 1.01, 2006. Available online: http://cell.scei.co.jp/pdf/CBE_Architecture_v101.pdf.

  3. Wang, X., & Ziavras, S. G. (2003). “Performance optimization of an FPGA-based configurable multiprocessor for matrix operations,” Proc. Field-Programmable Technology (FPT), pp. 303–306.

  4. Borgio, S., Bosisio, D., Ferrandi, F., Monchiero, M., Santambrogio, M. D., Sciuto, D., et al. (2006).“Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA,” International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp. 107–114.

  5. Benini, L., & De Micheli, G. (2002). Networks on chips: a new SoC paradigm. Computer, 35(1), 70–78.

    Article  Google Scholar 

  6. Kim, M., Kim, D., & Sobelman, G. E. (2005). MPEG-4 Performance analysis for a CDMA network-on-chip. Proc. 2005 International Conference on Communications, Circuits and Systems, 1, 493–496.

    Article  Google Scholar 

  7. Denolf, K., Chirila-Rus, A., Turney, R., Schumacher, P., Vissers. K. (2005). Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs. Proc. International Conference on Field Programmable Logic and Applications, pp. 391–396.

  8. Kulmala, A., Lehtoranta, O., Hämäläinen, T. D., Hännikäinen, M. (2006). “Scalable MPEG-4 Encoder on FPGA Multiprocessor SoC,” EURASIP Journal on Embedded Systems, 15 pages. DOI 10.1155/ES/2006/38494.

  9. Salminen, E., Kangas, T., Hämäläinen, T. D., Riihimäki, J., Lahtinen, V., & Kuusilinna, K. (2006). HIBI Communication network for system-on-chip. Journal of VLSI Signal Processing, 43(2–3), 185–205 Springer Netherlands, Jun.

    MATH  Google Scholar 

  10. Kulmala, A., Salminen, E., Hännikäinen, M., Hämäläinen, T. D. (2006).Evaluating SoC Network Performance in MPEG-4 Encoder. Proc. IEEE 2006 Workshop on Signal Processing, pp. 271–276.

  11. Pande, P. P., Grecu, C., Jones, M., Ivanov, A., & Sales, R. (2005). Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Transactions on Computers, 54(8), 1025–1040.

    Article  Google Scholar 

  12. Bolotin, E., Cidon, I., Ginosar, R., & Kolodny, A. (2004). Cost considerations in network on chip. Integration, the VLSI Journal, 38(1), 19–42.

    Article  Google Scholar 

  13. Xu, J., Wolf, W., Henkel, J., Chakradhar, S., & Lv, T. (2004). A case study in networks-on-chip design for embedded video. Proc. Design, Automation and Test in Europe Conference and Exhibition, 2, 770–775.

    Google Scholar 

  14. Zeferino, C. A., Kreutz, M. E., Carro, L., Susin, A. A. (2002). “A study on communication issues for Systems-on-Chip.” Proc. 15th Symposium on Integrated Circuits and Systems Design, pp. 121–126.

  15. Dumitrascu, F., Bacivarov, I., Pieralisi, L., Bonaciu, M., & Jerraya, A. A. (2006). Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. Proc. Design, Automation and Test in Europe, 02, 1–6.

    Google Scholar 

  16. Pimentel, A. D., Polstra, S., Terpstra, F., van Halderen, A. W., Coffland, J. E., Hertzberger, L. O. (2002). “Towards efficient design space exploration of heterogeneous embedded media systems,” Embedded processor design challenges: systems, architectures, modeling, and simulation, pp. 57–73.

  17. Angiolini, F., Meloni, P., Carta, S., Benini, L., Raffo, L. (2006). “Contrasting a NoC and a traditional interconnect fabric with layout awareness,” Proc. Conference on Design, Automation and Test in Europe, IEEE, Mar. pp. 1–6.

  18. Kumar, R., Zyuban, V., Tullsen, D. M. (2005). “Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling,” Proc. International Symposium on Computer Architecture, pp. 408–419.

  19. Thid, R., Millberg, M., Jantsch, A. (2003). “Evaluating NoC communication backbones with simulation,” Proc. of the IEEE NorChip Conference, pp. 27–30.

  20. Liang, J., Laffely, A., Srinivasan, S., & Tessier, R. (2004). An architecture and compiler for scalable on-chip communication. IEEE Transactions on Very Large Scale Integration Systems, 12(7), 711–726.

    Article  Google Scholar 

  21. Shen, J.-S., Chang, K.-C., Chen, T.-F. (2006). “On a design of crossroad switches for low-power on-chip communication architectures,” Proc.. 2006 IEEE International Symposium on Circuits and Systems, pp. 477–480.

  22. Hilton, C., & Nelson, B. (2005). “A flexible circuit switched NOC for FPGA based systems,” Proc. International Conference on Field Programmable Logic and Applications, pp. 191–196.

  23. Kreutz, M. E., Carro, L., Zeferino, C. A., Susin, A. A. (2001). “Communication architectures for system-on-chip,” Proc. 14th Symposium on Integrated Circuits and Systems Design, pp. 14–19.

  24. Thid, R., Sander, I., Jantsch, A. (2006). “Flexible bus and noc performance analysis with configurable synthetic workloads,” in DSD, pp. 681–688.

  25. Kulmala, A., Hämäläinen, T. D., Hännikäinen, M. (2006). “Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA,” Proc. 9th Euromicro Conference on Digital System Design, pp. 83–86.

  26. Kulmala, A., Hämäläinen, T. D., Hännikäinen, M. (2006). “Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA”, Proc. 16th International Conference on Field Programmable Logic and Applications, pp. 495–500.

  27. Kulmala, A., Salminen, E., Hämäläinen, T. D. (2006). Distributed Bus Arbitration Algorithm Comparison on FPGA Based MPEG-4 Multiprocessor SoC,” Proc. Norchip 2006, pp. 167–170.

  28. Rasmus, A., Kulmala, A., Salminen, E., Hämäläinen, T. D. (2007). “IP Integration Overhead Analysis in System-on-Chip Video Encoder”, Proc. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 333–336.

  29. Kulmala, A., Salminen, E., Hämäläinen, T. D. (2007). “Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder”, Proc. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 105–110.

  30. Kulmala, A., Salminen, E., Hämäläinen, T. D. (2007). “Prototyping and Evaluating Large System-on-Chips on Multi-FPGA Platform”, International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS), pp. 179–189.

  31. Vanne, J., Aho, E., Hämäläinen, T. D., & Kuusilinna, K. (2006). A High-Performance Sum of Absolute Difference Implementation for Motion Estimation. IEEE Transactions on Circuits and Systems for Video Technology, 16(7), 876–883.

    Article  Google Scholar 

  32. Altera Corporation, “Stratix II Device Handbook, Volume 1,” version SII5V1–1.1, July 2004.

  33. Atific Ltd., “Atific MPEG-4 Video Encoder Software & Products,” 25.10.2006, available online: http://www.atific.fi/video.

  34. Salminen, E., Kangas, T., Lahtinen, V., Riihimäki, J., Kuusilinna, K., & Hämäläinen, T. D. (2007). Benchmarking mesh and hierarchical bus networks in system-on-chip context. Journal of Systems Architecture, 53(8), 477–488 Aug.

    Article  Google Scholar 

  35. Xu, J., Wolf, W., Henkel, J., Chakradhar, S. (2005). “Methodology for Design, Modeling, and Analysis of Networks-on-Chip”, Proc. The IEEE International Symposium on Circuits and Systems, pp. 1778–1781.

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Acknowledgements

This work has been supported by Emil Aaltonen Foundation, Tuula and Yrjö Neuvo fund, Nokia Foundation, Ulla Tuominen foundation, and TUT Graduate School. The authors would like to acknowledge M.Sc. Antti Rasmus and Mr. Hannu Penttinen for their contribution on developing the MPSoC architecture and MPEG-4 software.

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  1. Department of Computer Systems, Tampere University of Technology, P.O. Box 553, Korkeakoulunkatu 1, 33101, Tampere, Finland

    Ari Kulmala, Erno Salminen, Marko Hännikäinen & Timo D. Hämäläinen

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  1. Ari Kulmala
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  2. Erno Salminen
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  3. Marko Hännikäinen
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  4. Timo D. Hämäläinen
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Correspondence to Ari Kulmala.

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Kulmala, A., Salminen, E., Hännikäinen, M. et al. Evaluating SoC Network Performance in MPEG-4 Encoder. J Sign Process Syst Sign Image Video Technol 56, 105–123 (2009). https://doi.org/10.1007/s11265-008-0227-1

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