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Low Complexity Decoder Architecture for Low-Density Parity-Check Codes

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Abstract

In this paper, we propose a low complexity decoder architecture for low-density parity-check (LDPC) codes using a variable quantization scheme as well as an efficient highly-parallel decoding scheme. In the sum-product algorithm for decoding LDPC codes, the finite precision implementations have an important tradeoff between decoding performance and hardware complexity caused by two dominant area-consuming factors: one is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of the nonlinear function Ψ(x). The proposed variable quantization schemes offer a large reduction in the hardware complexities for LUT and memory. Also, an efficient highly-parallel decoder architecture for quasi-cyclic (QC) LDPC codes can be implemented with the reduced hardware complexity by using the partially block overlapped decoding scheme and the minimized power consumption by reducing the total number of memory accesses for updated messages. For (3, 6) QC LDPC codes, our proposed schemes in implementing the highly-parallel decoder architecture offer a great reduction of implementation area by 33% for memory area and approximately by 28% for the check node unit and variable node unit computation units without significant performance degradation. Also, the memory accesses are reduced by 20%.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, 55455, USA

    Daesun Oh & Keshab K. Parhi

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  1. Daesun Oh
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  2. Keshab K. Parhi
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Correspondence to Daesun Oh.

Additional information

This work was supported by the Army Research Office under grant number W911NF-04-1-0272.

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Oh, D., Parhi, K.K. Low Complexity Decoder Architecture for Low-Density Parity-Check Codes. J Sign Process Syst Sign Image Video Technol 56, 217–228 (2009). https://doi.org/10.1007/s11265-008-0231-5

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  • DOI: https://doi.org/10.1007/s11265-008-0231-5

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