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Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer

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Abstract

The flexibility and programmability of SDR come at the expense of reduced efficiency and increased energy consumption. This is usually considered as the penalty of SDR. However, the flexibility and programmability have great potentials for improving the system-wide efficiency if they are properly exploited. In this paper, we present a HSDPA chip equalizer that is explicitly designed for SDR implementations. The first SDR-specific feature of our work is the multi-mode operation based on heterogeneous algorithms. The proposed equalizer combines an optimized LMS variant (with subspace-aware extension) and an optimized SRI-RLS algorithm based on QRD. Instead of always applying the powerful SRI-RLS algorithm, the equalizer switches to simple LMS-variant when possible. With negligible BER degradation, the multi-mode operation can reduce 60% of the cycle-count on TI TMS320C6713 for 3GPP case 4 with 16QAM modulation. The proposed equalizer framework also incorporates a generic, robust and efficient scheme for equalization-length adaptation. The length-adaptation scheme can make very fast run-time decision based on an efficient policy-template, which is optimized with large training set at design time. We test 14 representative channel profiles specified in ITU-R M.1225, 3GPP TR 25.943 and 3GPP TS 25.101. Comparing to worst-case based design the length-adaptation achieves more than 10× cycle-count reductions for ten of the cases.

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Authors and Affiliations

  1. Division of Nomadic Embedded Systems, IMEC, Kapeldreef-75, Leuven, 3001, Belgium

    Min Li, Bruno Bougard, Liesbet Van Der Perre & Francky Catthoor

Authors
  1. Min Li
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  2. Bruno Bougard
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  3. Liesbet Van Der Perre
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  4. Francky Catthoor
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Correspondence to Min Li.

Additional information

Part of the paper appeared in IEEE SIPS 2006 and IEEE ICASSP 2007.

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Li, M., Bougard, B., Van Der Perre, L. et al. Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer. J Sign Process Syst Sign Image Video Technol 56, 327–340 (2009). https://doi.org/10.1007/s11265-008-0232-4

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  • DOI: https://doi.org/10.1007/s11265-008-0232-4

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