Abstract
In this paper we present a low complexity discrete cosine transform (DCT) architecture based on computation re-use in vector-scalar product. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified and shared to reduce computational complexity in 1-D DCT operation. Compared to general distributed arithmetic based DCT architecture, the proposed DCT shows 38% of area and 18% of power savings with little performance degradation. We also propose an efficient method to trade off image quality for computational complexity. The approach is based on the modification of DCT bases in bit-wise manner and different computational complexity/image quality trade-off levels are suggested. Finally, based on the above approaches, we propose a low complexity DCT architecture, which can dynamically reconfigure from one trade-off level to another. The reconfigurable DCT architecture can achieve power savings ranging from 28% to 56% for 3 different trade-off levels.
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Appadwedula, S., Goel, M., Shanbhag, N. R., Jones, D. L., & Ramchandran, K. (2001). Total system energy minimization for wireless image transmission. Journal of VLSI Signal Processing, 27, 99–117.
Lan, T., & Tewfik, A. (1997). Adaptive low power multimedia wireless communications. Conference on information sciences and systems (pp. 377–382).
ITU-T Recommendation T.81. (1992). Digital compression and coding of continuous-tone still images, September.
Park, J., Kwon, S., & Roy, K. (2002). Low power reconfigurable DCT design based on sharing multiplication. IEEE international conference on acoustics, speech and signal processing (ICASSP) (Vol. 3, pp. 3116–3119), May.
Park, J., & Roy, K. (2004). A low power reconfigurable DCT architecture to trade off image quality for computational complexity. IEEE international conference on acoustics, speech and signal processing (ICASSP) (Vol. 5, pp. 17–20), May.
Chen, W. A., Harrison, C., & Fralick, S. C. (1977). A fast computational algorithm for the discrete cosine transform. IEEE Transactions on Communications, COM-25(9), 1004–1009, September.
Wang, Z. (1984). Fast algorithms for the discrete W-Transform and for the discrete fourier transform. IEEE Transactions on Acoustics, Speech, and Signal Processing, ASSP-32(4), 803–816, August.
Vetterli, M., & Nussbaumer, H. (1984). Simple FFT and DCT Algorithms with reduced number of operations. Signal Processing, 6(4), 267–278 (North Holland), August.
Lin, B. Y., Sung, C. C., Ruan, S. J., & Shie, M. C. (2005). Novel DCT architecture for quality and power efficient. IEEE International Workshop on Nonlinear Signal and Image Processing (NSIP) (pp. 151–156), May.
Shams, A. M., Chidanandan, A., Pan, W., & Bayoumi, M. A. (2006). NEDA: A low-power high-performance DCT architecture. IEEE Transactions on Signal Processing, 54(3), 955–964, March.
White, S. A. (1989). Applications of distributed arithmetic to digital signal processing: A tutorial review. IEEE ASSP Magazine (pp. 4–19), July.
Yu, S., & Swartzlander, E. E. Jr. (2001). DCT implementation with distributed arithmetic. IEEE Transactions on Computers, 50(9), 985–991, September.
Xanthopoulos, T., & Chandrakasan, A. P. (2000). A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization. IEEE Journal of Solid-State Circuits, 35(5), 740–750 May.
Lin, C. P., Tseng, P. C., & Chen, L. G. (2005). Nearly lossless content-dependent low-power DCT design for mobile video applications. IEEE international conference on multimedia and expo (ICME) (Vol. 6–6, pp. 1238–1241), July.
Parhi, K. K., & Messerschmitt, D. G. (1991). Static rate-optimal scheduling of iterative data flow programs via optimum unfolding. IEEE Transactions on Computers, 40(20), 178–195, February.
Parhi, K. K. (1999). VLSI digital signal processing systems: Design and implementation. New York: Wiley.
Taylor, C. N., & Dey, S. (2001). Adaptive image compression for enabling mobile multimedia communication. In Proc. IEEE international conference on communications (ICC) (Vol. 6, pp. 1925–9), June.
Sinha, A., Wang, A., & Chandrakasan, A. (2002). Energy scalable system design. IEEE Transactions on VLSI Systems, 10(2), 135–145, April.
Bracamonte, J., Ansorge, M., & Pellandini, F. (1996). VLSI systems for image compression. A power consumption/image resolution trade-off approach. In Proc. of conf. on digital compression technologies and systems for video communication SPIE (Vol. 2952, pp. 591–596). Berlin, Germany, 7–11 October.
Park, J., Jeong, W., Mahmoodi, H., Wang, Y., Choo, H., & Roy, K. (2004). Computation sharing programmable FIR filter for high performance and low power applications. IEEE Journal of Solid States Circuits (JSSC), 39(2), 348–357, February.
Rao, K. R., & Yip, P. (1990). Discrete cosine tranform: Algorithms, advantages, applications. Boston: Academic.
Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2002). Digital integrated circuits: A design perspective (2nd ed.). Englewood Cliffs: Prentice Hall.
Weste, N., & Eshraghian, K. (1994) Principles of CMOS VLSI design: A systems perspective (2nd ed.). Boston: Addison Wesley.
Synopsys, Inc. (2001). Nanosim reference guide. Mountain View: Synopsys, Inc., June.
Synopsys, Inc. (1999). PathMill reference guide. Mountain View: Synopsys, Inc., May.
Cadence, Inc. (2003). Envisia silicon ensemble place-and-route reference. San Jose: Cadence, Inc.
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Park, J., Roy, K. A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption. J Sign Process Syst Sign Image Video Technol 53, 399–410 (2008). https://doi.org/10.1007/s11265-008-0242-2
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DOI: https://doi.org/10.1007/s11265-008-0242-2