Abstract
Timing recovery in communication systems with linear modulations is usually performed with a non-data-aided feedback loop based on a fractional interpolator timing corrector and the Gardner’s timing error detector. The contribution of this paper is twofold. First, some design rules are given to predict the behaviour of the loop if pipeline is used. Second, it is shown that pipelining can be used to reduce power consumption in a timing feedback loop. A timing recovery loop has been implemented in an FPGA device and power consumption measures indicates that by including 16 extra registers in the loop the power consumption decreases a 63% and the synchronizer can process up to 66.5 MSPS.
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Acknowledgements
This research was supported by FEDER, the Spanish Ministerio de Educación y Ciencia, under Grant No. TEC2005-08406-C03-01 and Generatitat Valenciana, under Grant No. GV06/114.
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Torres, V., Pérez-Pascual, A., Sansaloni, T. et al. Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. J Sign Process Syst Sign Image Video Technol 56, 17–23 (2009). https://doi.org/10.1007/s11265-008-0252-0
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DOI: https://doi.org/10.1007/s11265-008-0252-0