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Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications

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Abstract

This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC or 46% lower than multipartite approach.

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Acknowledgements

This research was supported by FEDER, the Spanish Ministerio de Educación y Ciencia, under Grant No. TEC2005-08406-C03-01 and Generatitat Valenciana, under Grant No. ACOMP/202

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Authors and Affiliations

  1. Department of Physics and Computer Architecture, Miguel Hernandez University, 03202, Elche, Alicante, Spain

    R. Gutierrez

  2. Department of Electronic Engineering, Polytechnic University of Valencia, 46730, Grao de Gandía, Valencia, Spain

    J. Valls

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  1. R. Gutierrez
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  2. J. Valls
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Correspondence to R. Gutierrez.

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Gutierrez, R., Valls, J. Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications. J Sign Process Syst Sign Image Video Technol 56, 25–33 (2009). https://doi.org/10.1007/s11265-008-0253-z

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  • DOI: https://doi.org/10.1007/s11265-008-0253-z

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