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Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers

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Abstract

IEEE-754 rounding support increases the critical delay for floating-point multipliers. Except round-to-zero mode all IEEE rounding modes test the (n − 2) least significant product bits for one. The result of the test is indicated by the sticky-bit. Since fast generation of the sticky-bit is critical for performance, various sticky-bit generation designs are developed. This paper presents a comparison of previous fast sticky-bit generation designs and proposes a novel design that is independent from the multiplier’s hardware. Thus, the proposed design can be used in any floating-point multiplier or any floating-point multiply-accumulate circuit. The proposed method is one of the fastest among all methods and it uses the minimum hardware resources among the designs that use the same idea.

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Notes

  1. The draft IEEE standard for IEEE floating-point arithmetic can be accessed at http://754r.ucbtest.org.

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Authors and Affiliations

  1. Elec. and Eln. Eng. Dept., Cukurova University, Balcali, 01330, Adana, Turkey

    Mustafa Gök

  2. Comp. Eng. Dept., Mersin University, Çiftlikköy, 33342, Mersin, Turkey

    Metin Mete Özbilen

Authors
  1. Mustafa Gök
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  2. Metin Mete Özbilen
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Correspondence to Mustafa Gök.

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Gök, M., Özbilen, M.M. Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers. J Sign Process Syst Sign Image Video Technol 56, 51–57 (2009). https://doi.org/10.1007/s11265-008-0258-7

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  • DOI: https://doi.org/10.1007/s11265-008-0258-7

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