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Compiling for Reduced Bit-Width Queue Processors

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Abstract

Embedded systems are characterized by the requirement of demanding small memory footprint code. A popular architectural modification to improve code density in RISC embedded processors is to use a reduced bit-width instruction set. This approach reduces the length of the instructions to improve code size. However, having less addressable registers by the reduced instructions, these architectures suffer a slight performance degradation as more reduced instructions are required to execute a given task. On the other hand, 0-operand computers such as stack and queue machines implicitly access their source and destination operands making instructions naturally short. Queue machines offer a highly parallel computation model, unlike the stack model. This paper proposes a novel alternative for reducing code size by using a queue-based reduced instruction set while retaining the high parallelism characteristics in programs. We introduce an efficient code generation algorithm to generate programs for our reduced instruction set. Our algorithm successfully constrains the code to the reduced instruction set with the addition of only 4% extra code, in average. We show that our proposed technique is able to generate about 16% more compact code than MIPS16, 26% over ARM/Thumb, and 50% over MIPS32 code. Furthermore, we show that our compiler is able to extract about the same parallelism than fully optimized RISC code.

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Authors and Affiliations

  1. IBM Tokyo Research Laboratory, 1623-14 Shimotsuruma, Yamato-shi, Kanagawa-ken, 242-8502, Japan

    Arquimedes Canedo

  2. University of Aizu, Aizu-Wakamatsu, Fukushima-ken, 965-8580, Japan

    Ben A. Abderazek

  3. University of Electro-Communications, 1-5-1 Chofugaoka, Chofu-Shi, Tokyo, 182-8585, Japan

    Masahiro Sowa

Authors
  1. Arquimedes Canedo
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  2. Ben A. Abderazek
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  3. Masahiro Sowa
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Correspondence to Arquimedes Canedo.

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Canedo, A., Abderazek, B.A. & Sowa, M. Compiling for Reduced Bit-Width Queue Processors. J Sign Process Syst Sign Image Video Technol 59, 45–55 (2010). https://doi.org/10.1007/s11265-008-0286-3

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  • DOI: https://doi.org/10.1007/s11265-008-0286-3

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