Abstract
A power and area efficient 108-bit end-around carry adder is implemented using IBM 65nm SOI technology. The adder is used for a multiply-add fused (MAF) floating point unit. Careful balance of the adder structure and structure-aware layout techniques enabled this adder to have a latency of 270ps at power consumption of 20mW with 1V supply.
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Authors would like to thank Kevin Nowka and Martin Schmookler for their valuable discussions and suggestions.
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Zhang, X.Y., Chan, YH., Montoye, R. et al. A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit. J Sign Process Syst Sign Image Video Technol 58, 139–144 (2010). https://doi.org/10.1007/s11265-008-0325-0
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DOI: https://doi.org/10.1007/s11265-008-0325-0