Skip to main content
SpringerLink
Log in

A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

The design space exploration (DSE) problem addressed in this paper is to find out Multi-Processor System-on-Chip architectures for a given multi-task signal processing application aiming to minimize the system cost while satisfying the real-time constraints. It involves the following three sub-problems: selecting processing elements, mapping an application to the processing elements, and determining the communication architecture. The proposed approach consists of two inner design loops: one is a cosynthesis loop that determines the selection of PEs and the mapping of a given application to the PEs, and the other is a communication architecture synthesis loop to find the hierarchical shared bus architecture. We specify an application with a synchronous data flow (SDF) model of computation that has well-matched semantics with the algorithmic function flow in DSP applications. To solve the problem, we need to compare the estimated performance of design points and choose the best ones. The common method of simulation-based performance estimation is too time-consuming to explore the wide design space. Thanks to the analytical properties of the SDF model, the performance estimation can be done without HW/SW cosimulation in both loops. A global feedback from the communication architecture synthesis step to the cosynthesis step forms the proposed DSE framework. We use a real-life application, 4-channel Digital Video Recorder (DVR) that is a multi-task example, as well as randomly generated graphs to show the viability of the proposed approach.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15

Similar content being viewed by others

Notes

  1. The terms ‘function block’, ‘block’, and ‘node’ are used interchangeably.

  2. The terms ‘inter-processor communication’ and ‘inter-PE communication’ are used interchangeably.

  3. f/s is the abbreviation of frames/second.

References

  1. Keutzer, K., Malik, S., Newton, R., Rabaey, J., & Sangiovanni-Vincentelli, A. (2000). “System-level design: Orthogonalization of concerns and platform-based design”. IEEE Transactions on Computer-Aided Design, 19(12), 1523–1543.

    Article  Google Scholar 

  2. Lee, E., & Messerschmitt, D. (1987). Synchronous data flow. Proceedings of IEEE, 75(9), 1235–1245.

    Article  Google Scholar 

  3. Kim, D., Ha, S., Gupta, R. (2006). Parallel co-simulation using virtual synchronization with redundant host execution. In Proceedings of the Design Automation and Test in Europe, pp 1151–1156.

  4. Oh, H., Ha, S. (2002) A hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints. In Proceedings of the. International Workshop on Hardware/Software Codesign, pp. 133–138.

  5. Kim, S., & Ha, S. (2006). Efficient exploration of bus-based system-on-chip architectures. IEEE Transactions on Very Large Scale Integration Systems, 14(7), 681–692. doi:10.1109/TVLSI.2006.878260.

    Article  Google Scholar 

  6. Vallejo, M. L., & Lopez, J. C. (2003). On the hardware-software partitioning problem: system modeling and partitioning techniques. ACM Transactions on Design Automation of Electronic Systems, 8(3), 269–297. doi:10.1145/785411.785412.

    Article  Google Scholar 

  7. Hu, J., & Marculescu, R. (2005). Energy- and performance-aware mapping for regular NoC architectures. IEEE Transactions on Computer-Aided Design, 24(4), 551–562.

    Article  Google Scholar 

  8. Hansson, A., Goossens, K., & Radulescu, A. (2007). A unified approach to mapping and routing on a Network-on-Chip for both best-effort and guaranteed service traffic. VLSI Design, 2007, 68432.

    Google Scholar 

  9. Pimentel, A. D., Erbas, C., & Polstra, S. (2006). A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Transactions on Computers, 55(2), 99–112. doi:10.1109/TC.2006.16.

    Article  Google Scholar 

  10. Pasricha, S., & Dutt, N. (2007). A framework for co-synthesis of memory and communication architectures for MPSoC. IEEE Transactions on Computer-Aided Design, 26(3), 408–420.

    Article  Google Scholar 

  11. Murali, S., Benini, L., & De Micheli, G. (2007). An application-specific design methodology for on-chip crossbar generation. IEEE Transaction on Computer-Aided Design, 26(7), 1283–1296.

    Article  Google Scholar 

  12. Bertozzi, D., Jalabert, A., Murali, S., Tamhankar, R., Stergiou, S., Benini, L., & De Micheli, G. (2005). NoC synthesis flow for customized domain specific multiprocessor Systems-on-Chip. IEEE Transactions on Computer-Aided Design, 16(2), 113–129.

    Google Scholar 

  13. Lahiri, K., Raghunathan, A., & Dey, S. (2004). Design space exploration for optimizing on-chip communication architectures. IEEE Transactions on Computer-Aided Design, 23(6), 952–961.

    Article  Google Scholar 

  14. Henia, R., Hamann, A., Jersak, M., Racu, R., Richter, K., & Ernst, R. (2005). System level performance analysis—the SymTA/S approach. IEE Proceedings Computers & Digital Techniques, 152(2), 148–166. doi:10.1049/ip-cdt:20045088.

    Article  Google Scholar 

  15. Givargis, T., & Vahid, F. (2002). Platune: A tuning framework for System-on-a-Chip platforms. IEEE Transactions on Computer-Aided Design, 21(11), 1317–1327.

    Article  Google Scholar 

  16. Knudsen, P. V., & Madsen, J. (1999). Integrating communication protocol selection with hardware/software Codesign. IEEE Transactions on Computer-Aided Design, 18(8), 1077–1095.

    Article  Google Scholar 

  17. Thepayasuwan, N., & Doboli, A. (2005). Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed. IEEE Transactions on Very Large Scale Integration System, 13(5), 525–538. doi:10.1109/TVLSI.2004.842910.

    Article  Google Scholar 

  18. Lieverse, P., Wolf, P. V., Deprettere, E., & Vissers, K. (2001). A methodology for architecture exploration of heterogeneous signal processing systems. Journal of VLSI Signal Processing Systems, 29(3), 197–207. doi:10.1023/A:1012231429554.

    Article  MATH  Google Scholar 

  19. Oh, H., & Ha, S. (2004). Fractional rate dataflow model for memory efficient synthesis. Journal of VLSI Signal Processing Systems, 37(1), 41–51. doi:10.1023/B:VLSI.0000017002.91721.0e.

    Article  Google Scholar 

  20. Park, C., & Ha, S. (2002). Extended synchronous dataflow for efficient DSP systems prototyping. Design Automation for Embedded Systems, 6(3), 295–322. doi:10.1023/A:1014070804761.

    Article  Google Scholar 

  21. Kim, Y.-J., & Kim, T. (2006). A HW/SW partitioner for multi-mode multi-task embedded applications. Journal of Signal Processing Systems, 44(3), 269–283.

    MATH  Google Scholar 

  22. Kappagantula, V., Mahapatra, R.N. (2003). PAP: Power-aware partitioning of reconfigurable systems. In Proc. International Symposium on High Performance Computer Architecture on SSRS.

  23. Schmitz, M. T., A-Hashimi, B. M., & Eles, P. (2005). Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities. IEEE Transactions on Computer-Aided Design, 24(2), 153–169.

    Article  Google Scholar 

  24. Banerjee, S., Dutt, N. (2004). Efficient search space exploration for HW-SW partitioning. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, pp. 122–127.

  25. Wiangtong, T., Cheung, P., & Luk, W. (2002). Comparing three heuristic search methods for functional partitioning in hardware–software codesign. Design Automation for Embedded Systems, 6(4), 425–449. doi:10.1023/A:1016567828852.

    Article  Google Scholar 

  26. Dick, R. P. (2002). Multiobjective synthesis of low-power real-time distributed embedded systems. Ph.D. dissertation, Princeton University.

  27. Liu, J., & Lee, E. A. (2003). Timed multitasking for real-time embedded software. IEEE Control Systems Magazine, 23(1), 65–75. doi:10.1109/MCS.2003.1172830.

    Article  Google Scholar 

  28. Kim, S., Im, C., & Ha, S. (2005). Schedule-aware performance estimation of communication architecture for efficient design space exploration. IEEE Transactions on Very Large Scale Integration System, 13(5), 539–552. doi:10.1109/TVLSI.2004.842912.

    Article  Google Scholar 

  29. Lahiri, K., Raghunathan, A., & Dey, S. (2001). System-level performance analysis for designing system-on-chip communication architecture. IEEE Transactions on Computer-Aided Design, 20(6), 768–783.

    Article  Google Scholar 

  30. Thiele, L., Chakraborty, S., Gries, M., Maxiaguine, A., Greutert, J. (2001). Embedded software in network processors—models and algorithms. In Proceedings of the International Workshop on Embedded Software, pp. 416–434.

  31. SymTA/S. Symtavision Inc. http://www.symtavision.com/symtas.html

  32. Thiele, L., Chakraborty, S., Gries, M., Kunzli, S. (2002). A framework for evaluating design tradeoffs in packet processing architectures. In Proceedings of the Design Automation Conference, pp. 880–885.

  33. Pasricha, S., Dutt, N., Bozorgzadeh, E., & Ben-Romdhane, M. (2006). FABSYN: Floorplan-aware bus architecture synthesis. IEEE Transactions on Very Large Scale Integration System, 14(3), 241–253. doi:10.1109/TVLSI.2006.871763.

    Article  Google Scholar 

  34. Hwang, H., Oh, T., Jung, H., Ha, S. (2006). Conversion of Reference C Code to Dataflow Model: H.264 Encoder Case Study. in Proceedings of the Asia and South Pacific Design Automation Conference, pp.24–27.

  35. Yi, Y., Kim, D., & Ha, S. (2007). “Fast and accurate cosimulation of MPSoC using trace-driven virtual synchronization”. IEEE Transactions on Computer-Aided Design, 26(12), 2186–2200.

    Article  Google Scholar 

  36. Kwon, S., Lee, C., Kim, S., Yi, Y., Ha, S. (2004). Fast design space exploration framework with an efficient performance estimation technique. In Proceedings of the Workshop on Embedded Systems for Real Time Multimedia, pp. 27–32.

  37. Advanced Micro Bus Architecture, ARM (AMBA), http://www.arm.com/products/solutions/AMBAHomePage.html.

  38. Ha, S., Kim, S., Lee, C., Yi, Y., Kwon, S., & Joo, Y. (2007). PeaCE: A hardware–software codesign environment for multimedia embedded systems. ACM Transactions on Computer Systems, 12(3), 24. doi:10.1145/1255456.1255461.

    Google Scholar 

  39. Dave, B. P., Lakshminarayana, G., Jha, N.K. (1997). COSYN: Hardware–software co-synthesis of embedded systems. In Proceedings of the Design Automation Conference, pp. 703–708.

  40. Yen, T.-Y. (1996). Hardware-software co-synthesis of distributed embedded systems. Ph.D. dissertation, Princeton University.

  41. Hou, J., Wolf, W. (1996). Process partitioning for distributed embedded systems. In Proceedings of the International Workshop on Hardware/Software Codesign, pp. 70–76.

  42. Dick, R. P., Rhodes, D. L., Wolf, W. (1998). TGFF: Task Graphs for Free,” In Proceedings of the International Workshop on Hardware/Software Codesign, pp. 97–101.

  43. ARM, Ltd: RealView ARMulator. http://www.arm.com/products/DevTools/RealViewDevSuite.htm.

  44. Mentor Graphics, Inc.: ModelSim. http://www.mentor.com/products/fv/digital_verification/modelsim_se/index.cfm.

Download references

Acknowledgement

This work was supported by BK21 project and Acceleration Research sponsored by KOSEF research program (R17-2007-086-01001-0). The ICT and ISRC at Seoul National University and IDEC provided the research facilities for this study.

Author information

Authors and Affiliations

  1. School of Electrical Engineering and Computer Science, Seoul National University, Seoul, South Korea

    Choonseung Lee, Sungchan Kim & Soonhoi Ha

Authors
  1. Choonseung Lee
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Sungchan Kim
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Soonhoi Ha
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sungchan Kim.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Lee, C., Kim, S. & Ha, S. A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification. J Sign Process Syst Sign Image Video Technol 58, 193–213 (2010). https://doi.org/10.1007/s11265-009-0351-6

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-009-0351-6

Keywords

Search

Navigation