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A Multi-Shared Register File Structure for VLIW Processors

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Abstract

The available instruction level parallelism allowed by current register file organizations is not always fully exploited by media processors when running a multimedia application. This paper introduces a novel register file organization, called multi-shared register file, that eliminates this superfluous instruction scheduling flexibility by reducing the number of read and write ports and partitioning the register file in a special ring structure. A parameterized generic VLIW architecture is used to explore different configurations of our proposed register file structure in terms of estimated silicon area, minimum clock period, estimated power consumption, and multimedia task processing performance. Moreover, a metric highly related to multimedia applications is introduced to study trade-offs between hardware cost and performance. The results show that by substituting a monolithic register file with an equivalent multi-shared register file, the estimated area and the power consumption are considerably reduced at the cost of a negligible performance degradation.

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Acknowledgements

The authors thank Prof. Dr.-Ing. Holger Blume for the given comments in the review process.

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Authors and Affiliations

  1. Institute of Microelectronic Systems, Leibniz Universität Hannover, Hannover, Germany

    Guillermo Payá-Vayá, Javier Martín-Langerwerf & Peter Pirsch

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  1. Guillermo Payá-Vayá
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Correspondence to Guillermo Payá-Vayá.

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Payá-Vayá, G., Martín-Langerwerf, J. & Pirsch, P. A Multi-Shared Register File Structure for VLIW Processors. J Sign Process Syst Sign Image Video Technol 58, 215–231 (2010). https://doi.org/10.1007/s11265-009-0355-2

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