Abstract
With the de facto transformation of technology into nano-technology, more and more functional components can be embedded on a single silicon die, thus enabling high degree pipelining operations such as those required for multimedia applications. In recent years, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with multiple processors, on-chip memories, standard peripherals, and other functional blocks. The communication between these IP blocks is becoming the dominant critical system path and performance bottleneck of system-on-chip designs. Network-on-chip architectures, such as Virtual Channel (2004), Black-bus (2004), Pirate (2004), AEthereal (2005), and VICHAR (2006) architectures, emerged as promising solutions for future system-on-chip communication architecture designs. However, these existing architectures all suffer from certain problems, including high area cost and communication latency and/or low network throughput. This paper presents a novel network-on-chip architecture, Pipelining Multi-channel Central Caching, to address the shortcomings of the existing architectures. By embedding a central cache into every switch of the network, blocked head packets can be removed from the input buffers and stored in the caches temporally, thus alleviating the effect of head-of-line and deadlock problems and achieving higher network throughput and lower communication latency without paying the price of higher area cost. Experimental results showed that the proposed architecture exhibits both hardware simplicity and system performance improvement compared to the existing network-on-chip architectures.
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References
http://www.itrs.net/, accessed May 2007.
Hemani, A., Jantsch, A., Kumar, S., Postula, A., Oberg, J., Millberg, M., et al. (2000). Network on chip: An architecture for billion transistor era. In Proc IEEE Conf NorChip, Turku, Finland, 166–173.
Benini, L., & Micheli, G. D. (2002). Networks on chips: A new SOC paradigm. IEEE Transactions on Computers, 35(1), 70–78.
McKeown, N., & Anderson, T. E. (1998). A quantitative comparison of scheduling algorithms for input-queued switches. Computer Networks and ISDN Systems, 30(24), 23–26. doi:10.1016/S0169-7552(98) 00157-3.
McKeown, N. (1999). iSLIP: A scheduling algorithm for input-queued switches. IEEE/ACM Transactions on Networking, 7(2), 188–201. doi:10.1109/90.769767.
Gupta, P., & McKeown, N. (1999). Designing and implementing of a fast crossbar scheduler. IEEE Microwave Magazine, 19(1), 20–28. doi:10.1109/40.748793.
Karol, M., Hluchyj, M., & Morgan, S. (1987). Input versus output queueing on a space-division packet switch. IEEE Transactions on Community, 35(12), 1347–1356. doi:10.1109/TCOM.1987.1096719.
Zeferino, C. A., & Susin, A. A. (2003). SoCIN: A parametric scalable network-on-chip. In Proc IEEE Conf SBCCI 03’, Sao Paulo, Brazil, 169–174.
Clouard, A. (2003). Using transaction-level models in a SOC design flow. In W. Muller, W. Rosenstiel, & J. Ruf (Eds.), SystemC: Methodologies and applications (pp. 29–63). Kluwer Academic.
Wang, N., Sanusi, A., & Bayoumi, M. A. (2006). CTCNOC: A central caching network-on-chip communication architecture design. In Proc Conf IP/SOC-2006, Grenoble, France, 49–52.
Wang, N., Sanusi, A., Zhao, P., Mohamed, S., & Bayoumi, M. A. (2007). PMCNOC: A pipelining multi-channel central caching network-on-chip communication architecture design. In Proc IEEE Conf SIPs 07’, Shanghai, China, 487–492.
Guerrier, P., Greiner, A. (2000). A generic architecture for on-chip packet switched interconnections. In Proc IEEE Conf DATE 2000, Paris, France, 250-256
Kumar, S., Jantsch, A., Soininen, J., Forsell, M., Millberg, M., Oberg, J., et al. (2002). A network-on-chip architecture and design methodology. In Proc IEEE Conf ISVLSI 02’, Pittsburgh, 117–124.
Pande, P. P., Grecu, C., Jones, M., Ivanov, A., & Saleh, R. (2005). Performance evaluation and design trade-offs for network-on-chip interconnect architecture. IEEE Transactions on Computers, 54(8), 1025–1040. doi:10.1109/TC.2005.134.
Hahanov, V., Yegorov, O., & Mostova, K. (2007). Verification challenges of NOC architecture. In Proc IEEE Conf CAD System in Microelectronics, Polyana, Ukraine, 266–269.
Lahiri, K. (2003). On-chip communication: system-level architectures and design methodologies. PhD thesis, University of California, San Diego, USA.
Vermeulen, B., Dielissen, J., Goossens, K., & Ciordas, C. (2003). Bring communication networks on chip: Test and verification implications. IEEE Communications Magazine, 41(9), 74–81. doi:10.1109/MCOM.2003.1232240.
Lee, A. S., & Bergmann, N. W. (2003). On-chip communication architectures for reconfigurable system-on-chip. In Proc IEEE Conf FPT 03’, Tokyo, Japan, 332–335.
Zhao, D., & Wang, Y. (2006). MTNET: Design and optimization of a wireless SOC test framework. In Proc IEEE Int Conf SOCC’06, Austin, 239–242.
Henkel, J., Wolf, W., & Chakradhar, S. (2004). On-chip networks: a scalable, communication-centric embedded system design paradigm. In Proc IEEE int Conf VLSI Design, Mumbai, India, 845–851.
Beigne, E., Clermidy, F., Vivet, P., Renaudin, M., & Clouard, A. (2005). An asynchronous NOC architecture providing low latency service and its multi-level Design framework. In Proc IEEE Conf ASYNC 05’, New York City, 54–63.
Dally, W. J., & Towles, B. (2001). Route packets, not wires: On-chip interconnection networks. In Proc IEEE Conf DAC 01’, Las Vegas, 684–689.
Lee, S., Lee, C., & Lee, H. (2004). A new multi-channel on-chip-bus architecture for system-on-chips. In Proc IEEE Int Conf SOCC 04’, Santa Clara, 305–308.
Goossens, K., Dielissen, J., & Radulescu, A. (2005). AEthereal network-on-chip: Concepts, architectures and implementations. Proc. IEEE Design & Test of Computers, 22(5), 414–421. doi:10.1109/MDT.2005.99.
Anjo, K., Yamada, Y., Koibuchi, M., Jouraku, A., & Amano, H. (2004). BLACK-BUS: A new data-transfer technique using local address on networks-on-chip. In Proc IEEE 18th IPDPS’04, Santa Fe, 1063–1071.
Kavaldjiev, N., Smit, G., & Jansen, P. G. (2004). A virtual channel router for on-chip networks. In Proc IEEE Int Conf SOCC 04’, Santa Clara, 289–293.
Palermo, G., & Silvano, C. (2004). PIRATE: A framework for power/performance exploration of network-on-chip architectures. In Proc Int Conf PATMOS 04’, Santorini, Greece, 15–17.
Nicopoulos, C. A., Park, D., & Kim, J. (2006). ViChaR: A dynamic virtual channel regulator for network-on-chip routers. In Proc IEEE Conf MICRO’06, Orlando, 333–346.
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Wang, N., Sanusi, A., Zhao, P.Y. et al. PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design. J Sign Process Syst 60, 315–331 (2010). https://doi.org/10.1007/s11265-009-0379-7
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DOI: https://doi.org/10.1007/s11265-009-0379-7