Skip to main content
SpringerLink
Log in

Accurate Area, Time and Power Models for FPGA-Based Implementations

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family (Deng et al. 2008). These models are designed to facilitate efficient design space exploration in an automated algorithm-architecture codesign framework. Detailed models for estimating the number of slices, block RAMs and 18×18-bit multipliers for fixed point and floating point IP cores have been developed. These models are also utilized to develop power models that consider the effect of logic power, signal power, clock power and I/O power. Timing models have been developed to predict the latency of the fixed point and floating point IP cores. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error is quite small for single IP cores; the error for the area estimate, for instance, is on the average 0.95%. The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption. The proposed models have also been integrated into a hardware-software partitioning tool to facilitate design space exploration under area and time constraints.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Figure 1
Figure 2
Figure 3

Similar content being viewed by others

References

  1. Deng, L., Sobti, K., & Chakrabarti, C. (2008). Accurate models for estimating area and power of FPGA implementations. In IEEE int. conf. on acoustics, speech, and signal processing—(ICASSP), pp. 1417–1420.

  2. MATLAB (2007). The MATLAB website. http://www.mathworks.com.

  3. Zergainoh, N.-E., Tambour, L., Urard, P., & Jerraya, A. A. (2006). Macrocell builder: IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems. EURASIP Journal on Applied Signal Processing, 2006(14), 1–11.

    Google Scholar 

  4. Atat, Y., & Zergainoh, N. E. (2007). Simulink-based MPSoC design: New approach to bridge the gap between algorithm and architecture design. In IEEE computer society annual symposium on VLSI, pp. 9–14.

  5. Xilinx (2007). System generator for DSP. Xilinx Webpage. http://www.xilinx.com/ise/optional_prod/system_generator.htm.

  6. Banerjee, P., et al. (2004). Overview of a compiler for synthesizing MATLAB programs onto FPGAs. IEEE Transactions on VLSI Systems, 12, 312–323.

    Google Scholar 

  7. Nordin, G., Milder, P. A., Hoe, J. C., & Puschel, M. (2005). Automatic generation of customized discrete Fourier transform IPs. In Proceedings of the 42nd design automation conference—(DAC), pp. 471–474.

  8. Nayak, A., Haldar, M., Choudhary, A., & Banerjee, P. (2002). Accurate area and delay estimators for FPGAs. In Proceedings of the design, automation and test conference in Europe—(DATE), pp. 862–869.

  9. Bjuréus, P., Millberg, M., & Jantsch, A. (2002). FPGA resource and timing estimation from Matlab execution traces. In Proceedings of the international symposium on hardware/software codesign—(CODES), pp. 31–36.

  10. Xu, M., & Kurdahi, F. (1996). Area and timing estimation for lookup table based FPGAs. In Proceedings of the European conference on design and test—(EDTC), pp. 151–157.

  11. Enzler, R., Jeger, T., Cottet, D., & Troster, G. (2000). High-level area and performance estimation of hardware building blocks on FPGAs. In Proceedings of international workshop on field-programmable logic and applications - (FPL), pp. 525–534.

  12. Chen, D., Cong, J., & Fan, Y. (2003). Low-power high-level synthesis for FPGA architectures. In Proceedings of international symposium on low power electronics and design - (ISLPED), pp. 134–139.

  13. Poon, K. K. W., Yan, A., & Wilton, S. J. E. (2002). A flexible power model for FPGAs. In Proceedings of international conference on field-programmable logic and applications - (FPL), pp. 312–321.

  14. Amira, A., & Chandrasekaran, S. (2007). Power modeling and efficient FPGA implementation of FHT for signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15, 286–295.

    Article  Google Scholar 

  15. Milder, P. A., Ahmad, M., Hoe, J. C., & Puschel, M. (2006). Fast and accurate resource estimation of automatically generated custom DFT IP cores. In Proceedings of the international symposium on field programmable gate arrays, pp. 211–220.

  16. Kim, J. (2007). TANOR: A tool for accelerating N-body simulations on reconfigurable platform. In Proceedings of international conference on field programmable logic and applications - (FPL), pp. 68–73.

  17. Xilinx (2007). Logicore. Xilinx Webpage. http://www.xilinx.com/ipcenter/index.htm.

  18. Xilinx (2007). LogicoreAddSub. The Xilinx webpage. www.xilinx.com/ipcenter/catalog/logicore/docs/addsub.pdf.

  19. Sherrod, P. H. (2005). Nonlinear regression analysis program. http://www.nlreg.com/NLREG.pdf.

  20. Xilinx (2007). Xpower. The Xilinx Xpower webpage. http://www.xilinx.com/products/design_tools/logic_design/verification/xpower.htm.

  21. Sobti, K. (2007). Efficient function evaluations with lookup tables for structured matrix operations. In Proceedings of the IEEE workshop on signal processing systems - (SiPS), pp. 463–468.

  22. Kim, J. (2008). High performance signal processing on reconfigurable platforms. Ph.D. thesis, Pennsylvania State University, State College.

  23. Zhang, Y., et al. (2008). Compiler directed hierarchical hardware-software mapping for algorithm-architecture codesign. In Grace hopper celebration of women in computing- (GHC), p. 36.

  24. Makino, J. (2006). The GRAPE project. Computing in Science and Engineering, 8(1), 30–40.

    Article  MathSciNet  Google Scholar 

Download references

Acknowledgements

This work was supported by a grant from DARPA W911NF-05-1-0248. The authors would like to thank the members of the FANTOM project, Dr. J.S. Kim, P. Mangalagiri, Dr. V. Narayanan and Dr. M. Kandemir of Computer Science and Engineering Department, Pennsylvania State University, C.L. Yu of Electrical Engineering Department, Arizona State University, and Dr. N. Pitsianis and Dr. X. Sun of Computer Science Department, Duke University, for their valuable help.

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Arizona State University, Phoenix, AZ, USA

    Lanping Deng, Kanwaldeep Sobti & Chaitali Chakrabarti

  2. Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA

    Yuanrui Zhang

Authors
  1. Lanping Deng
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kanwaldeep Sobti
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yuanrui Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Chaitali Chakrabarti
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Lanping Deng.

Additional information

This paper is an extension of the ICASSP’08 paper “Accurate Models for Estimating Area and Power of FPGA Implementations”.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Deng, L., Sobti, K., Zhang, Y. et al. Accurate Area, Time and Power Models for FPGA-Based Implementations. J Sign Process Syst 63, 39–50 (2011). https://doi.org/10.1007/s11265-009-0387-7

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-009-0387-7

Keywords

Search

Navigation