Skip to main content
Springer Nature Link
Log in

Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

This paper presents the algorithm and reconfigurable architecture of motion-adaptive deinterlacer for high-definition video. The content-adaptability of algorithm and the reconfiguration of architecture are concurrently explored by algorithm/architecture co-design methodology and Caltrop actor language (CAL) modeling of the dataflow. In the design methodology we employed, the CAL dataflow model is also very helpful in the verification of our deinerlacer. The proposed algorithm and architecture design of deinterlacer is more cost-efficient than two recently proposed works in terms of algorithmic performance and silicon area of VLSI implementation. Moreover, data path reconfiguration efficiently enables various interpolation schemes using less computational resource of hardware than non-reconfigurable architecture.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5

Similar content being viewed by others

Reference

  1. Bondalapati, K., & Prasanna, V. K. (2002). Reconfigurable computing systems. Proceedings of the IEEE, 90(7), 1201–1217.

    Article  Google Scholar 

  2. Nikolaos, S. V., & Konstantinos, M. (2005). System Level Design of Reconfigurable Systems-on-Chip. Secaucus, NJ: Springer.

    Google Scholar 

  3. Shoa, A., & Shirani, S. (2005). Run-time reconfigurable systems for digital signal processing applications: A survey. J VLSI Signal Process Syst Signal Image Video Technol, 39(3), 213–235. doi:10.1007/s11265-005-4841-x.

    Article  Google Scholar 

  4. Mei, B., De Sutter, B., Vander Aa, T., Wouters, M., Kanstein, A., & Dupont, S. (2008). Implementation of a coarse-grained reconfigurable media processor for AVC decoder. J Signal Process Syst, 51(3), 225–243. doi:10.1007/s11265-007-0152-8.

    Article  MATH  Google Scholar 

  5. Liang, L., McCanny, J. V., & Sezer, S. (2007). “Reconfigurable Video Motion Estimation Processor,” Proceedings of Anniversary IEEE International SOC Conference (pp. 55–58) Hsinchu, Taiwan.

  6. Vogt, T., & Wehn, N. (2008). A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment. IEEE Transactions on Very Large Scale Integrated System, 16(10), 1309–1320. doi:10.1109/TVLSI.2008.2002428.

    Article  Google Scholar 

  7. Veljanovski, R., Stojcevski, A., Singh, J., Zayegh, A., & Faulkner, M. (2003). A Low Cost Reconfigurable Architecture for a UMTS Receiver. IEICE Transactions on Communications, E86-B(12), 3441–3451.

    Google Scholar 

  8. Lee, G. G., Jang, E. S., Mattavelli, M., Tsai, C-J., Lucarz, C., Raulet, M., & Ding, D. (2008). “Text of ISO/IEC FCD 23001-4: Codec Configuration Representation,” ISO/IEC JCT1/SC29/WG11 MPEG w9772, Archamps, France, Apr. 2008.

  9. Tung, Y-S., Lee, G-G., Jang, E. S., Lee, S., Asai, K., Yamada Y., & Mattavelli, M. (2008). “FCD ISO/IEC 23002-4: Video Tool Library,” ISO/IEC JCT1/SC29/WG11 MPEG w9774, Archamps, France, Apr. 2008.

  10. de haan, G., & Bellers, E. B. (1998). Deinterlacing – an overview. Proceedings of the IEEE, 86(9), 1839–1857.

    Article  Google Scholar 

  11. Lee, G. G., Lin, H-Y., Su, D. W-C., & Wang, M-J. (2007). Multiresolution-Based Texture Adaptive Algorithm for High-Quality Deinterlacing. IEICE Transaction on Information and System, E 90-D(11).

  12. Chang, Y. L., Lin, S. F., Chen, L. G. (2004). Extended intelligent edge-based line average with its implementation and test method. Proc Int Symp Circuits Syst, 2 (May), II-341–II-344.

    Google Scholar 

  13. Kuo, C. J., Liao, C., & Lin, C. C. (1997). Adaptive interpolation technique for scanning rate conversion. IEEE Transactions on Circuits and System Video Technology, 7(3), 539–542. doi:10.1109/76.585932.

    Article  Google Scholar 

  14. Lee, G. G., Wang, M-J., Lin, H-Y., Su, D. W-C. & Lin, B-Y. (2007). Algorithm/Architecture Co-Design of 3D Spatio-Temporal Motion Estimation for Video Coding. IEEE Transactions on Multimedia, 9(3), Apr.

  15. Lee, G. G., Wang, M-J., Lin, H-Y. & Lai, R-L. On The Efficient Algorithm/Architecture Co-Exploration for Complex Video Processing. IEEE International Conference on Multimedia & Expo (ICME 2008).

  16. Khawam, S., Nousias, I., Milward, M., Yi, Y., Muir, M., & Arslan, T. (2008). The Reconfigurable Instruction Cell Array. IEEE Transactions on Very Large Scale Integrated System, 16(1), 75–85. doi:10.1109/TVLSI.2007.912133.

    Article  Google Scholar 

  17. Ansaloni, G., Bonzini, P., & Pozzi, L. (2008). Design and architectural exploration of expression-grained reconfigurable arrays. IEEE Symposium on Application Specific Processors, Anaheim Convention Center, California, June 8–9, 2008.

  18. Jung, S., & Kim, T. G. (2008). An operation and interconnection sharing algorithm for reconfiguration overhead reduction using static partial reconfiguration. IEEE Transactions on Very Large Scale Integrated System, 16(12), 1589–1595. doi:10.1109/TVLSI.2008.2000973.

    Article  Google Scholar 

  19. Moreano, N., Bonn, E., De Souza, C., & Araujo, G. (2005). Efficient Datapath Merging for Partially Reconfigurable Architectures. IEEE Transactions on Computer Aided Design of Integrated Circuit and System, 24(7), 969–980. doi:10.1109/TCAD.2005.850844.

    Article  Google Scholar 

  20. Lee, G. G., Wang, M-J., Li, H-T., & Lin, H-Y., “A Motion-Adaptive Deinterlacer via Hybrid Motion Detection and Edge-Pattern Recognition,” EURASIP Journal on Image and Video Processing, Volume 2008, Article ID 741290, 10 pages, Mar. 2008.

  21. Lee, H.Y., Park, J.W., Bae, T.M., Choi, S.U., Ho, Y. (2000). Ha, Adaptive scan rate up-conversion system based on human visual characteristics. IEEE Trans. Consum. Electron. 46(4).

  22. Yoo, H., & Jeong, J. (2002). Direction-oriented interpolation and its application to de-interlacing. IEEE Transaction on Consumer Electronics, 48(4), 954–962.

    Google Scholar 

  23. Gonzalez, R. C., & Woods, R. E. (2002). Digital Image processing. Upper Saddle River, NJ: Prentice-Hall.

    Google Scholar 

  24. Lee, G. G., Lin, H-Y., Wang, M-J., Lai, R-L., Jhuo, C. W. & Chen, B-H. "Spatial-Temporal Content-Adaptive Deinterlacing Algorithm,” IET Image processing, Vol. 2, No. 6, pp. 323–336, Dec. 2008.

  25. Eker, J. & Janneck, J. W. “An introduction to the Caltrop actor language,” available at: http://embedded.eecs.berkeley.edu/caltrop/index.html

  26. Lee, G. G., Lin, H-Y., Wang, M-J., Chen, B-H., & Cheng, Y-L. “On The Verification of Multi-Standard SOC’S for Reconfigurable Video Coding Based on Algorithm/Architecture Co-Exploration,” in Proc. of IEEE 2008 Workshop on Signal Processing Systems (SiPS 2008).

  27. Lin, C., Wei, C-J., Sheu, M., Chiang, H., & Liaw, C. (2006). “The VLSI Design of deinterlacing with scene change detection.” IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, May 21-24.

  28. Sun, H., Zheng, N., Ge, C., Wang, D., & Ren, P. “An efficient motion adaptive de-interlacing and its VLSI architecture design,” Proceedings of IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, Apr. 2008, pp. 455–458.

Download references

Author information

Authors and Affiliations

  1. Media SoC Lab., Department of Electrical Engineering, National Cheng Kung University, No.1, Ta-Hsueh Road, Tainan, 701, Taiwan, R.O.C.

    Gwo Giun Lee, Ming-Jiun Wang, Bo-Han Chen, JiunFu Chen, Ping-Keng Jao, Ching Jui Hsiao & Ling-Fei Wei

Authors
  1. Gwo Giun Lee
    View author publications

    You can also search for this author inPubMed Google Scholar

  2. Ming-Jiun Wang
    View author publications

    You can also search for this author inPubMed Google Scholar

  3. Bo-Han Chen
    View author publications

    You can also search for this author inPubMed Google Scholar

  4. JiunFu Chen
    View author publications

    You can also search for this author inPubMed Google Scholar

  5. Ping-Keng Jao
    View author publications

    You can also search for this author inPubMed Google Scholar

  6. Ching Jui Hsiao
    View author publications

    You can also search for this author inPubMed Google Scholar

  7. Ling-Fei Wei
    View author publications

    You can also search for this author inPubMed Google Scholar

Corresponding author

Correspondence to Ming-Jiun Wang.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Lee, G.G., Wang, MJ., Chen, BH. et al. Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design. J Sign Process Syst 63, 181–189 (2011). https://doi.org/10.1007/s11265-009-0388-6

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-009-0388-6

Keywords