Skip to main content

Advertisement

Springer Nature Link
Log in

Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

This paper presents a novel digital signal processing (DSP) unit including a new baseline wander (BLW) corrector to support fast Ethernet in twisted pair (TP) cable channels. The proposed DSP unit consists of a programmable gain amplifier (PGA), timing recovery loop, adaptive equalizer and the new BLW corrector. Unlike the existing BLW correctors, the proposed BLW corrector calculates the BLW error by subtracting the equalizer input from the slicer output. Moreover, the new BLW corrector implemented in the digital domain uses four symbols to remove the BLW instead of the two symbols used in previous works. In addition, the proposed adaptive equalizer uses 2−7 as the optimum step size, i.e., μ. Since μ is a multiple of 2, the equalizer eliminates the need for multipliers and, thus, has a small area and consumes less power. To verify the performance of the proposed DSP unit, floating-point and fixed-point simulations using the SPW™ tool were performed. The measured BER is less than 10−10 when the cable length is 150 m. The proposed DSP unit was modeled by Verilog-HDL and synthesized using the 0.18 μm SEC cell library. The implemented DSP unit having 128,528 gates can operate at 142.7 MHz.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

References

  1. IEEE. (2002). Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications. IEEE Std. 802.3.

  2. Gigabit Ethernet alliance. Gigabit Ethernet whitepaper, Available: http://www.gigabit-ethernet.org.

  3. Johns, D. A., & Essig, D. (1997). Integrated circuits for data transmission over twisted-pair channels. IEEE Journal of Solid-State Circuits, 32, 398–406.

    Article  Google Scholar 

  4. Lee, J. H., Park, W. H., Hong, J. H., Sunwoo, M. H., Kim, K. H. (2003). A high-speed blind DFE equalizer using an error feedback filter for QAM modems. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’ 2003), May 2003, 464–467.

  5. Yoo, K., Lee, H., Han, G. (2002). A low power CMOS adaptive line equalizer for Fast Ethernet. Proceedings of the IEEE Asia-Pacific Conference, Aug. 2002, 129–132.

  6. Everitt, J., Parker, J. F., Hurst, P., Nack, D., & Konda, K. R. (1998). A CMOS transceiver for 10-Mb/s and 100-Mb/s Ethernet. IEEE Journal of Solid-State Circuits, 33, 2169–2177.

    Article  Google Scholar 

  7. Shoval, A., Shoaei, O., Lee, K. O., Leonowich, R. H. (1999). A CMOS Mixed-signal 100Mb/s receive architecture for Fast Ethernet. Proceedings of the IEEE Integrated Circuits Conference, May 1999, 253–256.

  8. Intel corporation. LXT972A data sheet, Available: http://www.intel.com.

  9. Broadcom corporation. BMC5208 data sheet, Available: http://www.broadcom.com.

  10. Mysticom corporation. MystiPHY110 product brief, Available: http://www.mysticom.com.

  11. Buzes, M. (1999). Method and apparatus for reducing baseline wander. United States, Patent 6,140,857, Mar. 29, 1999.

  12. Lin, L. C.-L., & Chou, G. (2002). Automatic gain control for communication receivers. United States, Patent US 2003/0142659 A1, Jan. 25, 2002.

  13. Huss, S., Mullen, M., Gray, C. T., Smith, R., Summers, M, Shafer, J., et al. (2001) A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 μm CMOS technology. Proceedings of the IEEE Custom Integrated Circuits Conference, 135–138.

  14. Greiss, I., Lida, E. (2001). Digital base-band Receiver. United States, Patent US 2002/0021767 A1, Jun. 7, 2001.

  15. Raghavan, S. A. (1998). Digital baseline wander correction circuit. United States, Patent US 6,415,003 B1, Sep. 11, 1998.

  16. Lai, J.-T. (2002). Receiver for baseline wandering compensation. United States, Patent US 2003/0206604 A1, Jul. 12, 2002.

  17. Hong, J. H., & Sunwoo, M. H. (2007). Digital signal processor, receiver, corrector and methods for the same. United States Patent Pub. No. US 2007/0286315 A1, Dec. 13, 2007.

  18. Hong, J. H., & Sunwoo, M. H. (2006). Digital signal processor, receiver, corrector and methods for the same. Taiwan Patent Pub. No. 200627808, Aug. 1, 2006.

  19. Baek, J. H., Hong, J. H., Sunwoo, M. H. (2004). Efficient digital baseline wander algorithm and its architecture for fast Ethernet. Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2004, 136–141.

  20. Rivernider, J. Return loss and data transmission, Available: http://www.quabbin.com.

  21. Im, G. H., & Kim, D. H. (2001). All digital timing recovery and programmable gain amplifier controller for VDSL transmission. IEEE Transactions on Consumer Electronics, 47, 743–752.

    Article  Google Scholar 

  22. Mueller, K. H., & Muller, M. (1976). Timing recovery in digital synchronous data receivers. IEEE Transactions on Communications, COM-24, 516–531.

    Article  Google Scholar 

  23. Jones, D. L. (1992). Learning characteristics of transpose-form LMS adaptive filters. IEEE Transactions on Circuits and System II, 39, 745–1992.

    Article  MATH  Google Scholar 

Download references

Acknowledgements

This work was supported in part by the IT R&D program of MKE/KEIT [2009-F-010-01], in part by “system 2010” project of Korea Ministry of Knowledge Economy, and in part by the IDEC (IC Design Education Center).

Author information

Authors and Affiliations

  1. School of Electrical and Computer Engineering, Ajou University, San 5, Wonchun-Dong, Yeongtong-Ku, Suwon, 443-749, South Korea

    Juhyung Hong, Jaehyun Baek & Myung Hoon Sunwoo

Authors
  1. Juhyung Hong
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jaehyun Baek
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Myung Hoon Sunwoo
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Myung Hoon Sunwoo.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Hong, J., Baek, J. & Sunwoo, M.H. Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet. J Sign Process Syst 61, 193–204 (2010). https://doi.org/10.1007/s11265-009-0422-8

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-009-0422-8

Keywords

Search

Navigation