Skip to main content

Advertisement

Springer Nature Link
Log in

Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy and the throughput of the division operation, which makes it suitable for diverse applications with different requirements. Results show how various throughputs can be achieved under different maximum error and iteration limit configurations. Besides, the resource occupation is considerably small, compared with previous solutions.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Figure 1
Figure 2
Figure 3
Figure 4

Similar content being viewed by others

References

  1. Detrey, J., & Dinechin, F. (2007). A tool for unbiased comparison between logarithmic and floating-point arithmetic. Journal of VLSI Signal Processing Systems for Signal, 49(1), 161–175.

    Article  Google Scholar 

  2. Hormigo. J., Villalba, J., & Schulte, M. J. (2000). A hardware algorithm for variable-precision division. In Proceedings of the 4th conference on real numbers and computers.

  3. Flynn, M. J. (1970). On division by functional iteration. IEEE Transactions on Computers, C-19(8), 702–706.

    Article  Google Scholar 

  4. Valls, J., Kuhlmann, M., & Parhi, K. K. (2002). Evaluation of CORDIC algorithms for FPGA design. Journal of VLSI Signal Processing Systems for Signal, 32(3), 207–222.

    Article  MATH  Google Scholar 

  5. Wang, X., Braganza, S., & Leeser, M. (2006). Advanced components in the variable precision floating-point library. In Proc. 14th annual IEEE symposium on field-programmable custom computing machines FCCM ’06 (pp. 249–258).

  6. Obermann, S. F., & Flynn, M. J. (1997). Division algorithms and implementations. IEEE Transactions on Computers, 46(8), 833–854.

    Article  Google Scholar 

  7. Roesler, E., & Nelson, B. E. (2002). Novel optimizations for hardware floating-point units in a modern FPGA architecture. In FPL ’02: Proceedings of the reconfigurable computing is going mainstream, 12th international conference on field-programmable logic and applications (pp. 637–646). London: Springer.

    Chapter  Google Scholar 

  8. Wang, X., & Nelson, B. E. (2003). Tradeoffs of designing floating-point division and square root on virtex FPGAs. In Proc. 11th annual IEEE symposium on field-programmable custom computing machines FCCM 2003 (pp. 195–203).

  9. Sorokin, N. (2006). Implementation of high-speed fixed-point dividers on FPGA. Journal of Computer Science & Technology, 6(1), 8–11.

    Google Scholar 

  10. Ercegovac, M. D. & Muller, J.-M. (2003). Complex division with prescaling of operands. In Proc. IEEE international conference on application-specific systems, architectures, and processors (pp. 304–314).

  11. Arnold, M. G., & Collange, S. (2009). A dual-purpose real/complex logarithmic number system ALU. In Proc. 19th IEEE symposium on computer arithmetic ARITH 2009 (pp. 15–24).

  12. Liu, J., Weaver, B., & Zakharov, Y. (2008). FPGA implementation of multiplication-free complex division. Electronics Letters, 44(2), 95–96.

    Article  Google Scholar 

  13. Liu, J., Zakharov, Y. V., & Weaver, B. (2009). Architecture and FPGA design of dichotomous coordinate descent algorithms. IEEE Transactions on Circuits and Systems. 1, 56(11), 2425–2438.

    Article  MathSciNet  Google Scholar 

  14. Baines, R., & Pulley, D. (2003). A total cost approach to evaluating different reconfigurable architectures for baseband processing in wireless receivers. IEEE Communications Magazine, 41(1), 105–113.

    Article  Google Scholar 

  15. Gheorghiu, V., Kameda, S., Takagi, T., Tsubouchi, K., & Adachi, F. (2008). Implementation of frequency domain equalizer for single carrier transmission. In Proc. 4th international conference on wireless communications, networking and mobile computing WiCOM ’08 (pp. 1–5).

  16. Boher, L., Rabineau, R., & Helard, M. (2008). FPGA implementation of an iterative receiver for MIMO-OFDM systems. IEEE Journal on Selected Areas in Communications, 26(6), 857–866.

    Article  Google Scholar 

  17. Hestenes, M. R., & Stiefel, E. (1952). Methods of conjugate gradients for solving linear systems. Journal of Research of the National Bureau of Standards, 49, 409–436.

    MathSciNet  MATH  Google Scholar 

  18. Morris, G. R., Prasanna, V. K., & Anderson, R. D. (2006). A hybrid approach for mapping conjugate gradient onto an FPGA-augmented reconfigurable supercomputer. In Proc. 14th annual IEEE symposium on field-programmable custom computing machines FCCM ’06 (pp. 3–12).

  19. Sarraf, E. H., Ahmed-Ouameur, M., & Massicotte, D. (2007). FPGA design and implementation of direct matrix inversion based on steepest descent method. In Proc. 50th midwest symposium on circuits and systems MWSCAS 2007 (pp. 1213–1216).

  20. Yang, X., Sarkar, T. K., & Arvas, E. (1989). A survey of conjugate gradient algorithms for solution of extreme eigen-problems of a symmetric matrix. IEEE Transactions on Acoustics, Speech and Signal Processing, 37(10), 1550–1556.

    Article  MathSciNet  MATH  Google Scholar 

  21. Lopez-Martinez, F. J., del Castillo-Sanchez, E., Martos-Naya, E., & Entrambasaguas, J. T. (2009). Design and FPGA implementation of an OFDMA baseband modem for 3GPP-LTE physical layer. In Proc. digest of technical papers international conference on consumer electronics ICCE ’09 (pp. 1–2).

Download references

Acknowledgements

The authors would like to thank María García Abril for her collaboration in this project. This work is partially supported by the Spanish Government under project TEC2007-67289 and by the company AT4 Wireless.

Author information

Authors and Affiliations

  1. Departamento Ingeniería de Comunicaciones, Universidad de Málaga, Campus de Teatinos s/n, 29071, Málaga, Spain

    F. Javier López-Martínez, Eduardo del Castillo-Sánchez, José Tomás Entrambasaguas & Eduardo Martos-Naya

Authors
  1. F. Javier López-Martínez
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Eduardo del Castillo-Sánchez
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. José Tomás Entrambasaguas
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Eduardo Martos-Naya
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to F. Javier López-Martínez.

Rights and permissions

Reprints and permissions

About this article

Cite this article

López-Martínez, F.J., del Castillo-Sánchez, E., Entrambasaguas, J.T. et al. Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput. J Sign Process Syst 62, 319–324 (2011). https://doi.org/10.1007/s11265-010-0464-y

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-010-0464-y

Keywords