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Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

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Abstract

In order to develop a low-power and high-performance SoC platform for multimedia applications, the Parallel Architecture Core (PAC) project was initiated in Taiwan in 2003. A VLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed & ping-pong register organization and variable-length VLIW encoding, to a highly-configurable soft IP with several successful silicon implementations. A complete toolchain with an optimizing C compiler has also been developed for PACDSP. A dual-core PAC SoC has been designed and fabricated, which consists of a PACDSP core, an ARM9 core, scratchpad memories, and various on-chip peripherals, to demonstrate the outstanding performance and energy efficiency for multimedia processing such as the real-time H.264 codec. The first part of the two introductory papers of PAC describes the hardware architecture of the PACDSP core, its software development tools, and the PAC SoC with dynamic voltage and frequency scaling (DVFS).

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References

  1. Lin, T. J., Liu, C. N., Tseng, S. Y., Chu, Y. H., & Wu, A. Y. (2008). Overview of ITRI PAC project—from VLIW DSP processor to multicore computing platform. In Proc. VLSI-DAT, Apr. 2008, pp.188–191.

  2. Chang, C. W. et al. (2006). PACDSP core and application processors. In Proc. ICME, July 2006, pp.289–292.

  3. Lin, T. J., Hsiao, P. C., Chen, S. K., Kuo, Y. T., & Liu, C. W. (2008). Design & implementation of a high-performance & complexity-effective VLIW DSP for multimedia applications. Journal of Signal Processing Systems, 51, 209–223.

    Article  Google Scholar 

  4. http://www.itri.org.tw/

  5. Lapsley, P., Bier, J., & Lee, E. A. (1996). DSP Processor fundamentals—architectures and features. IEEE Press.

  6. Hu, Y. H. (2002). Programmable digital signal processors—architecture, programming, and applications. Marcel Dekker Inc.

  7. Fisher, J. A., Faraboschi, P., & Young, C. (2005). Embedded computing—A VLIW approach to architecture, compiler, and tools. Morgan Kaufmann.

  8. Lin, T. J., Hsiao, P. C., Liu, C. W., & Jen, C. W. (2006). Area-efficient register organization for fully-synthesizable VLIW DSP cores. International Journal of Electrical Engineering, 13, 117–127.

    Google Scholar 

  9. Lin, T. J., Lee, C. C., Liu, C. W., & Jen, C. W. (2005). A novel register organization for VLIW digital signal processors. In Proc. VLSI-TSA-DAT, Apr. 2005, pp.337–340.

  10. http://www.bdti.com/bdtimark/core_scores.pdf

  11. Lin, T. J. et al. (2005). A unified processor architecture for RISC & VLIW DSP. In Proc. GLSVLSI, Apr. 2005, pp.50–55.

  12. Liu, C. H. et al. (2005). Hierarchical instruction encoding for VLIW digital signal processors. In Proc. ISCAS, May 2005, pp.3503–3506.

  13. Wu, C. et al. (2006). Integrating compiler and system toolkit flow for embedded VLIW DSP processors. In Proc. RTCSA, Aug. 2006, pp.215–222.

  14. Lin, Y. C. et al. (2005). Compiler supports and optimizations for PAC VLIW DSP processors. In Proc. LCPC, Oct. 2005, pp.466–474.

  15. Chen, C. K. et al. (2007). Enabling compiler flow for embedded VLIW DSP processors with distributed register files. In Proc. LCTES, pp.146–148.

  16. http://ipf-orc.sourceforge.net/

  17. Wu, C. J., Chen, S. Y., & Lee, J. K. (2007). Copy propagation optimizations for VLIW DSP processors with distributed register files. Languages and Compilers for Parallel Computing (LNCS 4382), pp.251–266, Jun. 2007.

  18. Lin, Y. C., et al. (2008). Effective code generation for distributed and ping-pong register files: a case study on PAC VLIW DSP cores. Journal of Signal Processing Systems, 51, 269–288.

    Article  Google Scholar 

  19. Lin, Y. J., You, Y. P., & Lee, J. K. (2007). PALF: compiler supports for irregular register files in clustered VLIW DSP processors. Concurrency and Computation: Practice and Experience, 19, 2391–2406.

    Article  Google Scholar 

  20. Lu, C. H., Lin, Y. J., You, Y. P., & Lee, J. K. (2009). LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. Concurrency and Computation: Practice and Experience, 21, 101–114.

    Article  Google Scholar 

  21. Zivojnovic, V., Martinez, J., Schläger, C., & Meyr, H. (1994). DSPstone: a DSP-oriented benchmarking methodology. In Proc. ICSPAT, Oct. 1994.

  22. http://www.gnu.org/software/gdb/

  23. Eclipse Platform Technical Overview, available online: http://www.eclipse.org/articles/Whitepaper-Platform-3.1/eclipse-platform-whitepaper.pdf

  24. Hsieh, K. Y., Lin, Y. C., Huang, C. C., & Lee, J. K. (2008). Enhancing microkernel performance on VLIW DSP processors via multiset context switch. Journal of Signal Processing Systems, 51, 257–268.

    Article  Google Scholar 

  25. Lai, C. Y., Lin, J. H., & Wang, Y. F. (2005). DVFS SoC architecture and implementation. SoC Technology Journal, 3, 84–91.

    Google Scholar 

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Authors and Affiliations

  1. MediaTek Inc., Hsinchu, Taiwan

    David Chih-Wei Chang

  2. National Chiao Tung University, Hsinchu, Taiwan

    Tay-Jyi Lin

  3. National Tsing Hua University, Hsinchu, Taiwan

    Chung-Ju Wu & Jenq-Kuen Lee

  4. Industrial Technology Research Institute, Hsinchu, Taiwan

    Yuan-Hua Chu

  5. National Taiwan University, Taipei, Taiwan

    An-Yeu Wu

Authors
  1. David Chih-Wei Chang
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  2. Tay-Jyi Lin
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  3. Chung-Ju Wu
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  4. Jenq-Kuen Lee
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  5. Yuan-Hua Chu
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  6. An-Yeu Wu
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Correspondence to Tay-Jyi Lin.

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Chang, D.CW., Lin, TJ., Wu, CJ. et al. Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. J Sign Process Syst 62, 373–382 (2011). https://doi.org/10.1007/s11265-010-0470-0

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  • DOI: https://doi.org/10.1007/s11265-010-0470-0

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