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Low-Power Application-Specific Processor for FFT Computations

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Abstract

In this paper, a processor architecture tailored for radix-4 and mixed-radix FFT computations is described. The processor has native support for power-of-two transform sizes. Several optimizations have been used to improve the energy-efficiency of the processor and experiments show that a programmable solution can possess energy-efficiency comparable to fixed-function ASICs.

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Acknowledgement

This work has been supported in part by the Academy of Finland under funding decision 205743.

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Authors and Affiliations

  1. Department of Computer Systems, Tampere University of Technology, P.O. Box 553, 33101, Tampere, Finland

    Teemu Oskari Pitkänen & Jarmo Takala

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  1. Teemu Oskari Pitkänen
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  2. Jarmo Takala
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Correspondence to Teemu Oskari Pitkänen.

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Pitkänen, T.O., Takala, J. Low-Power Application-Specific Processor for FFT Computations. J Sign Process Syst 63, 165–176 (2011). https://doi.org/10.1007/s11265-010-0528-z

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  • DOI: https://doi.org/10.1007/s11265-010-0528-z

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