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Optimized Implementation of RNS FIR Filters Based on FPGAs

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Abstract

In this paper optimized Residue Number System (RNS) arithmetic blocks to better exploit some of the architectural characteristics of the last generation FPGAs are presented. The implementation of modulo m adders, modulo m constant and general multipliers, input and output converters are presented. These architectures are based on moduli sets chosen in order to optimally use the 6-input Look-Up Tables (LUTs) available in the Complex Logic Blocks (CLBs) of the new generation FPGAs. Experiments based on the implementation of Finite Impulse Response (FIR) filters characterized by different number of taps and wordlengths shows that the use of RNS together with suitable moduli sets optimally fits the 6-input LUTs in the last generation FPGAs architectures.

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Authors and Affiliations

  1. (ASI) Italian Space Agency, Viale Liegi, 26 00198, Rome, Italy

    Salvatore Pontarelli

  2. Department of Electronic Engineering, University of Rome “Tor Vergata”, Via del Politecnico 1, 00191, Rome, Italy

    Gian Carlo Cardarilli, Marco Re & Adelio Salsano

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  1. Salvatore Pontarelli
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  2. Gian Carlo Cardarilli
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  3. Marco Re
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  4. Adelio Salsano
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Correspondence to Salvatore Pontarelli.

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Pontarelli, S., Cardarilli, G.C., Re, M. et al. Optimized Implementation of RNS FIR Filters Based on FPGAs. J Sign Process Syst 67, 201–212 (2012). https://doi.org/10.1007/s11265-010-0537-y

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  • DOI: https://doi.org/10.1007/s11265-010-0537-y

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