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A Reconfigurable Channel Filter for Software Defined Radio Using RNS

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Abstract

This paper presents a high-speed FIR channel filter using residue number system (RNS) whose frequency response can be reconfigured to adapt to a multitude of channel filtering specifications of a multi-standard software defined radio (SDR) receiver. The channel filters in the channelizer of an SDR extract multiple narrowband channels corresponding to different communication standards from the wideband input signal. The proposed architecture has been synthesized on TSMC 0.18 μm CMOS standard cell technology. Synthesis result shows that the proposed reconfigurable FIR channel filter, for a Digital Advanced Mobile Phone Systems (D-AMPS) example, offers speed improvement of 42% and AT complexity reduction of 26% over existing reconfigurable FIR method.

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References

  1. Solla, T., & Vainio, O. (2002). Comparison of programmable FIR filter architectures for low power. In Proc. of 28th European Solid-State Circuits Conference (pp. 759–762), Sep. Firenze, Italy.

  2. Chen, K. H., & Chiueh, T. D. (2006). A low-power digit-based reconfigurable FIR filter. IEEE Transactions on Circuits and Systems II, 53(8), 617–621.

    Article  MATH  Google Scholar 

  3. Zhangwen, T., Zhang, J., & Min, H. (2002). A high-speed, programmable, CSD coefficient FIR filter. IEEE Transactions on Consumer Electronics, 48, 834–837.

    Article  Google Scholar 

  4. Demirsoy, S. S., Kale, I., Dempster, A. G. (2004). Efficient implementation of digital filters using novel reconfigurable multiplier blocks. In Proceedings of Thirty-Eighth Asilomar Conference on Signals, Systems and Computers (vol. 1, pp. 461–464).

  5. Tummeltshammer, P., Hoe, J. C., & Puschel, M. (2007). Time-multiplexed multiple-constant multiplication. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(9), 1551–1563.

    Article  Google Scholar 

  6. Mahesh, R., & Vinod, A. P. (2010). New reconfigurable architectures for implementing FIR filters with low complexity, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(2), 275–288.

    Article  Google Scholar 

  7. Szabo, N. S., & Tanaka, R. I. (1967). Residue arithmetic and its applications in computer technology. New York: McGraw-Hill.

    Google Scholar 

  8. Amondi, A., & Premkumar, B. (2007). Residue number systems-Theory and implementation, vol. 2. Imperial College Press.

  9. Base, U. M., Garcia, A., & Taylor, F. (2001). Implementation of a communications channelizer using FPGAs and RNS arithmetic. Journal of VLSI Signal Processing Systems, 28(1–2), 115–128.

    Article  Google Scholar 

  10. Bernocchi, G. L., Cardarilli, G. C., Del Re, A., & Nannarelli, A. (2006) A hybrid RNS adaptive filter for channel equalization. Fortieth Asilomar Conference on Signals, Systems and Computers, pp. 1706–1710, Oct.–Nov.

  11. Cadarilli, G. C., et al. (2002). Residue number system for reconfigurable datapath. In Proc. IEEE int. Symp. On Circuits and Syst., 2, 756–759.

  12. Menon, S., & Chang, C. H. (2006). A reconfigurable multi-modulus modulo multiplier. In Proc. IEEE Asia pacific conference on Circuits and Systems (pp. 1168–1171). Singapore, Dec.

  13. Soderstrand, M. A., & Al-Marayati, K. (1995). VLSI implementation of very-high-order FIR filters. IEEE International Symposium on Circuits and Systems, 2(30), 1436–1439.

    Google Scholar 

  14. Smitha, K. G., & Vinod, A. P. (2008). A reconfigurable high-speed RNS-FIR channel Filter for multi-standard software radio receivers. Proceedings of IEEE International Conference on Communication Systems, ICCS 2008, pp. 1354–1358, Nov.

  15. Zimmerman, R. (1999). Efficient VLSI implementation of modulo (2n+1) addition and multiplication. In Proc. 14th IEEE Symp. Computer Arithmetic (pp. 158–167). Apr.

  16. Efstathiou, C., Vergos, H. T., Dimitrakopoulos, G., & Nikolos, D. (2005). Efficient diminished-1 modulo 2n + 1 multipliers. IEEE Transactions on Computers, 54(4), 491–496.

    Article  Google Scholar 

  17. Vergos, H. T., & Efstathiou, C. (2007). Design of efficient modulo 2/sup n/ + 1 multipliers. IET Computers and Digital Techniques, 1(1), 49–57.

    Article  Google Scholar 

  18. Wang, Z., Jullien, G. A., & Miller, W. C. (1996). An efficient tree architecture for modulo 2n+ 1 multiplication. Journal of VLSI Signal Processing, 14, 241–248.

    Article  Google Scholar 

  19. Ma, Y. (1998). A simplified architecture for modulo (2n+1) multiplication. IEEE Transactions on Computers, 47(3), 333–337.

    Article  Google Scholar 

  20. Vinod, A. P., & M-K Lai, E. (2005). An efficient coefficient-partitioning algorithm for realizing low complexity digital filters. IEEE Transactions on Circuits and Systems II, 24, 1936–1946.

    Google Scholar 

  21. Proakis, J. G., & Manolakis, D. G. (1998). Design of digital filters. In Digital Signal Processing Principles, algorithms, and applications (pp. 614–738). Upper Saddle River: Prentice-Hall.

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Authors and Affiliations

  1. School of Computer Engineering, Nanyang Technological University, Nanyang Avenue, Singapore, 639798, Singapore

    K. G. Smitha & A. P. Vinod

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  1. K. G. Smitha
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  2. A. P. Vinod
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Correspondence to K. G. Smitha.

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Smitha, K.G., Vinod, A.P. A Reconfigurable Channel Filter for Software Defined Radio Using RNS. J Sign Process Syst 67, 229–237 (2012). https://doi.org/10.1007/s11265-010-0549-7

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  • DOI: https://doi.org/10.1007/s11265-010-0549-7

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