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CSD-RNS-based Single Constant Multipliers

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Abstract

Architectures for designing single constant multipliers in Residue Number System (RNS) for moduli of the 2n−1, 2n and 2n + 1 forms are introduced with the constant operand being recoded in Signed-Digit representation. Two methodologies are proposed. In the first one a straightforward implementation of the shift-and-add algorithm is adopted, while in the second one a graph-based approach is used. Both methodologies result in circuits that are shown to be efficient in terms of area and delay.

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References

  1. Ananda Mohan, P. V. (2002). Residue number systems: Algorithms and architectures. Norwell, MA: Kluwer Academic.

  2. Omondi, A., & Premkumar, B. (2007). Residue number systems: Theory and implementation. London: Imperial College Press.

  3. Chaves, R., & Sousa, L. (2003). RDSP: A RISC DSP based on residue number system. In: Proceedings of the 6th Euromicro Symposium on Digital System Design, (pp. 128–135) (September).

  4. Fernandez, P. G., & Lloris, A. (2003). RNS-based implementation of 8 × 8 point 2D-DCT over field-programmable devices. Electronics Letters, 39(1), 21–23.

    Article  Google Scholar 

  5. Ramirez, J., Meyer-Baese, U., Taylor, F., Garcia, A., & Lloris, A. (2003). Design and implementation of high-performance RNS wavelet processors using custom IC technologies. Journal of VLSI Signal Processing, 34(3), 227–237.

    Article  MATH  Google Scholar 

  6. Liu, Y., & Lai, E. (2004). Moduli set selection and cost estimation for RNS-based FIR filter and filter bank design. Design Automation for Embedded Systems, 9(2), 123–139.

    Article  Google Scholar 

  7. Marino, F., Stella, E., Branca, A., Veneziani, N., & Distante, A. (2001). Specialized hardware for real-time navigation. Real-Time Imaging, 7(1), 91–108.

    Article  Google Scholar 

  8. Meyer-Baese, U., Garcia, A., & Taylor, F. (2001). Implementation of a communications channelizer using FPGAs and RNS arithmetic. Journal of VLSI Signal Processing, 28(1–2), 115–128.

    MATH  Google Scholar 

  9. Panella, M., & Martinelli, G. (2003). An RNS architecture for quasi-chaotic oscillators. Journal of VLSI Signal Processing, 33(1–2), 199–220.

    MATH  Google Scholar 

  10. Conway, R., & Nelson, J. (2004). Improved RNS FIR filter architectures. IEEE Transactions on Circuits and Systems II, 51(1), 26–28.

    Article  Google Scholar 

  11. Navi, K., Molahosseini, A., & Esmaeildoust, M. (2010). How to teach residue number system to computer scientists and engineers. IEEE Transactions on Education, in press.

  12. Leibowitz, L. (1976). A simplified binary arithmetic for the Fermat number transform. IEEE Transactions on Acoustics, Speech, and Signal Processing, 24(5), 356–359.

    Article  MathSciNet  Google Scholar 

  13. Chaves, R., & Sousa, L. (2007). Improving residue number system multiplication with more balanced modulo sets and enhanced modular arithmetic structures. IET Computers and Digital Techniques, 1(5), 472–480.

    Article  Google Scholar 

  14. Vergos, H. T., & Bakalis, D. (2010). On implementing efficient modulo 2n + 1 arithmetic components. Journal of Circuits, Systems, and Computers, 19(5), 911–930.

    Article  Google Scholar 

  15. Avizienis, A. (1961). Signed-digit number representation for fast parallel arithmetic. IRE Transactions on Electronic Computers, EC-10(3), 389–400.

    Article  MathSciNet  Google Scholar 

  16. Parhami, B. (2000). Computer arithmetic: Algorithms and hardware designs. New York: Oxford University Press.

  17. Koren, I. (2002). Computer arithmetic algorithms, 2nd ed. Natick, MA: A K Peters.

  18. Hwang, K. (1979). Computer arithmetic: Principles, architecture and design. New York: Wiley.

  19. Wei, S., & Shimizu, K. (2000). Residue arithmetic circuits using a signed-digit number representation. In: Proceedings of IEEE International Symposium on Circuits and Systems, (pp. I-24–I-27) (May).

  20. Chen, S., & Wei, S. (2006). Weighted-to-residue and residue-to-weighted converters with three moduli (2n−1, 2n, 2n + 1) signed-digit architectures. In: Proceedings of IEEE International Symposium on Circuits and Systems (pp. 3365–3368) (May).

  21. Wei, S., & Shimizu, K. (2006). Modulo (2p±1) multipliers using a three-operand modular signed-digit addition algorithm. Journal of Circuits, Systems and Computers, 15(1), 129–144.

    Article  Google Scholar 

  22. Wei, S. (2008). A new residue adder with redundant binary number representation. In: Proceedings of the 6th International IEEE North–East Workshop on Circuits and Systems (pp. 157–160) (June).

  23. Lindstrom, A., Nordseth, M., Bengtsson, L., & Omondi, A. (2003). Arithmetic circuits combining residue and signed-digit representations. In: Proceedings of the 8th Asia-Pacific Computer Systems Architecture Conference (pp. 246–257) (September).

  24. Lindahl, A., & Bengtsson, L. (2005). A low-power FIR filter using combined residue and radix-2 signed-digit representation. In: Proceedings of the 8th Euromicro Conference on Digital System Design (pp. 42–47) (August).

  25. Persson, A., & Bengtsson, L. (2009). Forward and reverse converters and moduli set selection in signed-digit residue number systems. Journal of Signal Processing Systems, 56(1), 1–15.

    Article  Google Scholar 

  26. Potkonjak, M., Srivastava, M., & Chandrakasan, A. (1996). Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), 151–165.

    Article  Google Scholar 

  27. Boullis, N., & Tisserand, A. (2005). Some optimizations of hardware multiplication by constant matrices. IEEE Transactions on Computers, 54(10), 1271–1282.

    Article  Google Scholar 

  28. Voronenko, Y., & Puschel, M. (2007). Multiplierless multiple constant multiplication. ACM Transactions on Algorithms, 3(2).

  29. Gustafsson, O., Dempster, A. G., Johansson, K., Macleod, M. D., & Wanhammar, L. (2006). Simplified design of constant coefficient multipliers. Circuits, Systems and Signal Processing, 25(2), 225–251.

    Article  MathSciNet  MATH  Google Scholar 

  30. Gustafsson, O., & Wanhammar, L. (2007). Low-complexity constant multiplication using carry-save arithmetic for high-speed digital filters. In Proceeding of the 5th IEEE International Symposium on Image and Signal Processing and Analysis, (pp. 212–217) (September).

  31. Dimitrov, V., Imbert, L., & Zakaluzny, A. (2007). Multiplication by a constant is sublinear. In Proceedings of 18th IEEE Symposium on Computer Arithmetic, (pp. 261–268) (June).

  32. Thong, J., & Nicolici, N. (2009). Time-efficient single constant multiplication based on overlapping digit patterns. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(9), 1353–1357.

    Article  Google Scholar 

  33. Bakalis, D., & Vergos, H. T. (2009). Shifter circuits for 2n + 1, 2n, 2n–1 RNS. Electronics Letters, 45(1), 27–29.

    Article  Google Scholar 

  34. Kogge, P. M., & Stone, H. S. (1973). A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Transactions on Computers, 22(8), 786–792.

    Article  MathSciNet  MATH  Google Scholar 

  35. Kalampoukas, L., Nikolos, D., Efstathiou, C., Vergos, H. T., & Kalamatianos, J. (2000). High-speed parallel-prefix modulo 2n−1 adders. IEEE Transactions on Computers, 49(7), 673–680.

    Article  Google Scholar 

  36. Vergos, H. T., Efstathiou, C., & Nikolos, D. (2002). Diminished-one modulo 2n + 1 adder design. IEEE Transactions on Computers, 51(12), 1389–1399.

    Article  MathSciNet  Google Scholar 

  37. Tyagi, A. (1993). A reduced-area scheme for carry-select adders. IEEE Transactions on Computers, 42(10), 1163–1170.

    Article  Google Scholar 

  38. Altera FIR compiler, v.7.2.

  39. Efstathiou, C., Vergos, H. T., & Nikolos, D. (2003). Handling zero in diminished-one modulo 2n + 1 adders. International Journal of Electronics, 90(2), 133–144.

    Article  Google Scholar 

  40. Piestrak, S. (1994). Design of residue generators and multioperand modular adders using carry-save adders. IEEE Transactions on Computers, 43(1), 68–77.

    Article  Google Scholar 

  41. Molahosseini, A., Navi, K., Dadkhah, C., Kavehei, O., & Timarchi, S. (2010). Efficient reverse converter designs for the new 4-moduli sets 2n–1, 2n, 2n + 1, 22n + 1–1 and 2n–1, 2n + 1, 22n, 22n + 1 based on new CRTs. IEEE Transactions on Circuits and Systems I, 57(4), 823–835.

    Article  MathSciNet  Google Scholar 

  42. Shahana, T. K., Jose, B. R., James, R. K., Jacob, K. P., & Sasi, S. (2008). Dual-mode RNS based programmable decimation filter for WCDMA and WLANa. In Proceedings of IEEE Symposium on Circuits and Systems, (pp. 952–955) (May).

  43. Pai, C.-Y., Al-Khalili, A. J., & Lynch, W. E. (2003). Low-power constant-coefficient multiplier generator. Journal of VLSI Signal Processing, 35(2), 187–194.

    Article  MATH  Google Scholar 

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Authors and Affiliations

  1. Electronics Laboratory, Physics Department, University of Patras, Patras, Greece

    Evangelos Vassalos & Dimitris Bakalis

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  1. Evangelos Vassalos
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  2. Dimitris Bakalis
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Correspondence to Evangelos Vassalos.

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Vassalos, E., Bakalis, D. CSD-RNS-based Single Constant Multipliers. J Sign Process Syst 67, 255–268 (2012). https://doi.org/10.1007/s11265-010-0552-z

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  • DOI: https://doi.org/10.1007/s11265-010-0552-z

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