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1080p 60 Hz Intra-Frame Video CODEC Chip Design and Its Implementation

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Abstract

This paper presents a 1080p 60 Hz intra-frame CODEC system for zero delay AV streaming. For high quality streaming, the proposed CODEC employs an RGB-domain inter-color compensation algorithm using strong correlation between RGB color components which was previously presented by the authors of this paper. The proposed CODEC architecture is based on macroblock-level pipelining and parallel processing to handle a significant pixel rate of 1080p 60 Hz videos with RGB 4:4:4 format, i.e., 3 Gbps. Since syntax processing is a bottleneck to supporting speeds of up to 100 Mbps in real-time, a high performance context-adaptive variable length coding architecture exploiting the look-ahead technique is included in the proposed design. Also, the number of syntax symbols is adaptively restricted to accomplish zero end-to-end delay. Finally, by using MPEG-2 TS as the AV stream format, compatibility with general channel chips is guaranteed. Using TSMC 90 nm CMOS technology, the prototype chip is implemented with 1,208 K logic gates and 359 Kb internal SRAM. The chip can achieve real-time encoding and decoding of 1080p 60 Hz videos at 200 MHz execution speed in typical work conditions.

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Acknowledgements

This research was supported by DMC R&D Center, Samsung Electronics Co., Ltd, and was supported by the Defense Acquisition Program Administration and Agency for Defense Development, Korea, through the Image Information Research Center at Korea Advanced Institute of Science & Technology under the contract UD100006CD.

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Authors and Affiliations

  1. School of Electronic Engineering, Inha University, Incheon, Republic of Korea

    Byung Cheol Song

  2. Digital Media R&D Center, Samsung Electronics Co., Ltd, Suwon-City, Republic of Korea

    Yongseok Yi, Yun-Gu Lee, Nak-Hoon Kim, Jun Hyuk Ko, Tae Hee Kim, Dong Keun Lim, Woo Hyun Ju, Jae-Pil Moon & Kyunghwan Cho

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  1. Byung Cheol Song
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  2. Yongseok Yi
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Correspondence to Byung Cheol Song.

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Song, B.C., Yi, Y., Lee, YG. et al. 1080p 60 Hz Intra-Frame Video CODEC Chip Design and Its Implementation. J Sign Process Syst 67, 291–303 (2012). https://doi.org/10.1007/s11265-010-0564-8

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  • DOI: https://doi.org/10.1007/s11265-010-0564-8

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