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Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors

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Abstract

This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic. In addition, the dynamic power consumption can be reduced by as much as 15% by reducing memory accesses.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Illinois Institute of Technology, 3301 South Dearborn Street, Chicago, IL, 60616, USA

    Erdal Oruklu, Xin Xiao & Jafar Saniie

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  1. Erdal Oruklu
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  2. Xin Xiao
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  3. Jafar Saniie
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Correspondence to Erdal Oruklu.

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Oruklu, E., Xiao, X. & Saniie, J. Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors. J Sign Process Syst 66, 129–134 (2012). https://doi.org/10.1007/s11265-011-0586-x

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  • DOI: https://doi.org/10.1007/s11265-011-0586-x

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