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Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes

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Abstract

Low Density Parity-Check (LDPC) codes achieve the best performance when they are decoded with the sum-product (SP) algorithm. This is a two-phase iterative algorithm where two types of messages are interchanged and updated in each iteration. The group-shuffled or layered decoding schemes applied to the SP algorithm speed up its convergence by modifying its schedule, so they yield a reduction in the number of iterations required to achieve a given performance. However, the two-phase processing is still maintained. In this paper a modification of the group-shuffled scheme suitable for high-rate LDPC codes is proposed. The modification allows the overlapping of the two-phase computation, achieving a convergence speed up close to that of the group-shuffled scheme with higher throughput. Besides, high throughput architectures are presented for the modified algorithm. As an example, the proposed architecture has been implemented for the 2048-bit LDPC code of the IEEE 802.3an standard and it was synthesized in a 90 nm CMOS process achieving a throughput of 22.40 Gbps at 14 iterations with a clock frequency of 306 MHz and a total area of 10.5 mm2. Furthermore, the decoder performs within 0.5 dB of the floating-point 100 iterations sum-product algorithm at a PER of 10−5.

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Acknowledgements

This research was supported by Fondo Europeo de Desarrollo Regional (FEDER), the Spanish Ministerio de Ciencia e Innovación, under Grant No. TEC2008-06787.

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Correspondence to Javier Valls.

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Angarita, F., Sansaloni, T., Perez-Pascual, A. et al. Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes. J Sign Process Syst 68, 139–149 (2012). https://doi.org/10.1007/s11265-011-0592-z

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  • DOI: https://doi.org/10.1007/s11265-011-0592-z

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