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Design Methodology for Offloading Software Executions to FPGA

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Abstract

Field programmable gate array (FPGA) is a flexible solution for offloading part of the computations from a processor. In particular, it can be used to accelerate an execution of a computationally heavy part of the software application, e.g., in DSP, where small kernels are repeated often. Since an application code for a processor is a software, a design methodology is needed to convert the code into a hardware implementation, applicable to the FPGA. In this paper, we propose a design method, which uses the Transport Triggered Architecture (TTA) processor template and the TTA-based Co-design Environment toolset to automate the design process. With software as a starting point, we generate a RTL implementation of an application-specific TTA processor together with the hardware/software interfaces required to offload computations from the system main processor. To exemplify how the integration of the customized TTA with a new platform could look like, we describe a process of developing required interfaces from a scratch. Finally, we present how to take advantage of the scalability of the TTA processor to target platform and application-specific requirements.

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Authors and Affiliations

  1. Department of Computer Systems, Tampere University of Technology, P. O. Box 553, 33101, Tampere, Finland

    Tomasz Patyk, Perttu Salmela, Teemu Pitkänen, Pekka Jääskeläinen & Jarmo Takala

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  1. Tomasz Patyk
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  2. Perttu Salmela
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  3. Teemu Pitkänen
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  4. Pekka Jääskeläinen
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  5. Jarmo Takala
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Corresponding author

Correspondence to Tomasz Patyk.

Additional information

This work has been supported by the Academy of Finland under research grant decision 128126.

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Patyk, T., Salmela, P., Pitkänen, T. et al. Design Methodology for Offloading Software Executions to FPGA. J Sign Process Syst 65, 245–259 (2011). https://doi.org/10.1007/s11265-011-0606-x

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  • DOI: https://doi.org/10.1007/s11265-011-0606-x

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