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High-Speed Reconfigurable Parallel System to Design Good Error Correcting Codes in Communications

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Abstract

This paper presents a circuit that aids to accelerate the design of good error correcting codes in communications, where this design is a large optimization problem. The binary linear block codes detects and/or corrects the errors occurred during the data transmission. The problem to find a code that corrects a maximum number of errors is an optimization problem usually tackled by means of evolutionary algorithms and massive parallel computations. The circuit has been implemented on FPGA devices due to the easiness of the reconfigurable hardware to support real parallelism. The obtained results show that parallelizing the arithmetic operations involved in the fitness function improves the performance of a custom hardware solution in contrast to a software solution running on CPUs.

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Authors and Affiliations

  1. Department of Technologies of Computers and Communications, University of Extremadura, Escuela Politecnica, 10003, Caceres, Spain

    Juan A. Gómez-Pulido, Miguel A. Vega-Rodríguez & Juan M. Sánchez-Pérez

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  1. Juan A. Gómez-Pulido
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  2. Miguel A. Vega-Rodríguez
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  3. Juan M. Sánchez-Pérez
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Correspondence to Juan A. Gómez-Pulido.

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Gómez-Pulido, J.A., Vega-Rodríguez, M.A. & Sánchez-Pérez, J.M. High-Speed Reconfigurable Parallel System to Design Good Error Correcting Codes in Communications. J Sign Process Syst 66, 147–152 (2012). https://doi.org/10.1007/s11265-011-0626-6

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  • DOI: https://doi.org/10.1007/s11265-011-0626-6

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