Abstract
Dilation and erosion are two fundamental operations of mathematical morphology for image processing. This paper presents three hybrid wave-pipeline (HWP) architectures for real-time binary dilation operator. With minor changes to the number and/or to the type of the basic gates, they can be employed as erosion operator. In the first HWP-architecture, each single cell utilizes the wave technique along with delay units for balancing the data paths. By minimizing the number of delay units, the second HWP-architecture with reduced power consumption and hardware complexity is obtained. The third HWP-architecture employs wave technique in each three cascaded cells. This architecture improves the above performance further, at the cost of slight reduction in maximum clock frequency and clock frequency range. Simulation results, using a 0.18 μm CMOS technology, indicate that the HWP architectures have higher speed, less hardware complexity, and lower power consumption compared to pipeline (P) architecture. Also, they are faster than wave-pipeline (WP) architecture, without the difficulty of balancing the delay of long signal paths. Simulation illustrates that the third HWP-architecture dilates a 1024 × 1024 image by a 21 × 21 structuring element (SE) in 214.64 μs. The maximum frequency of operation is 5 GHz for the power supply of 1.8 V. The power dissipation is 410 mW, and the chip area is 0.075 mm2.

















Similar content being viewed by others
References
Serra, J. (1982). Image analysis and mathematical morphology. New York: Academic.
Yu, H. G. (2004). Morphological image segmentation for co-aligned multiple images using watersheds transformation, MS thesis, September.
Gonzalez, R. C., & Woods, R. E. (2002). Digital Image Processing, 2nd ed., Prentice Hall, Upper Saddle River, NJ.
Duff, M. (1979). Parallel processor for digital image processing. In P. Stucki (Ed.), Advances in digital image processing (pp. 265–279). New York: Plenum.
Batcher, K. E. (1980). Design of a massively parallel processor. IEEE Transactions on Computer, C-29, 836–840.
Wilson, S. (1985). The pixie-5000_A Systolic Array processor. In Proc. IEEE Comput. Soc. Workshop Comp. Architecture for pattern analysis and image database management, Miami Beach, FL, Nov. 18–20, pp. 477–483.
Kimmel, M. J., Jaffe, R. S., Mandeville, J. R., & Lavin, M. A. (1985). MITE: Morphic Image transform Engine, An Architecture for Reconfigurable Pipelines Of neighborhood Processor. In Proc. IEEE Comput. Soc. Workshop Comp. architecture For Pattern Analysis and Image Database Management, Miami Beach, FL, Nov. 18–20, pp. 493–500.
Lougheed, R. M., McCubbrey, D. L., & Sternberg, S. R. (1980). Cyto computer: Architectures for parallel image processing. In Proc. of the Workshop on picture Data Description and Management, Asilomar, CA, Aug. 27–28, pp. 281–286.
Loui, A. C. P., Venetsanopoulos, A. N., & Smith, K. C. (1992). Flexible architecture for morphological image processing and analysis. IEEE Transactions on Circuits and Systems for Video Technology, 2(1), 72–83.
Malamas, E. N., & Malamos, A. G. (2000). Fast implementation of binary morphological operations on hardware-efficient systolic architectures. Journal of VLSI Signal Processing, 25, 79–93.
Hedberg, H., Kristensen, F., Nilsson, P., & Owall, V. (2005). A low complexity architecture for binary image erosion and dilation using structuring element decomposition. IEEE International Symposium on Circuits and Systems (ISCAS), 4, 3431–3434.
Nyathi, J., & Delgado-Frias, J. G. (2002). A hybrid wave pipelined network router. IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, 49(12), 1764–1772.
Lowe, J. (2004). A high-performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks, MS Thesis, Washington State University School of Electrical Engineering and Computer Science, August.
Tatapudi, S. B., & Delgado-Frias, J. G. (2005) A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme, Intl. Conf. Computer Design (CDES), June.
Tatapudi, S. B., & Delgado-Frias, J. G. (2005). A high performance hybrid wave-pipelined multiplier. Proceedings of the IEEE Computer Society Annual Symp. on VLSI, New Frontiers in VLSI Design.
Burleson, W. P., Ciesielski, M., Klass, F., & Liu, W. (1998). Wave-pipelining: a tutorial and research survey. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(3), 464–474.
Acknowledgment
This work was supported in part by the Iran Telecommunication Research Center, ITRC, under contract T/500/12597, TMU-85-10-76.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Hajirahimi, M., Nabavi, A. & Kabir, E. Low-Power High-Speed Hybrid Wave-Pipeline Architectures for Binary Morphological Dilation. J Sign Process Syst 68, 391–399 (2012). https://doi.org/10.1007/s11265-011-0628-4
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-011-0628-4