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Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems

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Abstract

Designing accelerators for the real-time computation of Fast Fourier Transform (FFT) algorithms for state-of-the-art Orthogonal Frequency-Division Multiplexing (OFDM) demodulators has always been challenging. We have scaled-up a template-based Coarse-Grain Reconfigurable Array device for faster FFT processing that generates special purpose accelerators based on the user input. Using a basic and a scaled-up version, we have generated a radix-4 and mixed-radix (2, 4) FFT accelerator to process different length and types of algorithms. Our implementation results show that these accelerators satisfy not only the execution time requirements of FFT processing for Single Input Single Output (SISO) wireless standards that are IEEE-802.11 a/g and 3GPP-LTE but also for Multiple Input Multiple Output (MIMO) IEEE-802.11n standard.

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Authors and Affiliations

  1. Department of Computer Systems, Tampere University of Technology, P.O. Box 527, 33101, Tampere, Finland

    Waqar Hussain, Fabio Garzia, Tapani Ahonen & Jari Nurmi

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  1. Waqar Hussain
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  2. Fabio Garzia
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  3. Tapani Ahonen
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  4. Jari Nurmi
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Correspondence to Waqar Hussain.

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Hussain, W., Garzia, F., Ahonen, T. et al. Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems. J Sign Process Syst 69, 161–171 (2012). https://doi.org/10.1007/s11265-011-0642-6

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  • DOI: https://doi.org/10.1007/s11265-011-0642-6

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