Abstract
The narrow subcarrier spacing and wide bandwidth arrangement in the LTE downlink produce a vulnerability to sample clock mismatch between the transmitting and receiving data converters. Without high precision sampling clock frequencies, a high level of inter-carrier interference (ICI) is introduced, yielding undesirable performance. In this article, a method to jointly estimate and correct sampling frequency mismatch is proposed. The proposed method uses information already known to the receiver, operates strictly in the time domain and does not require the aid of pilot symbols or other frequency domain information. The method allows clocks with lower precision to be used with minimal performance degradation. Results are presented using MATLAB simulation as well as an FPGA hardware implementation.
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The authors would like to thank Innovative Integration for funding and equipment used in this research.
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This work has been presented at the 2011 Wireless Innovation Forum “SDR’11-WInnComm-Europe” conference [1].
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Briggs, E., Nutter, B. & McLane, D. Sample Clock Offset Detection and Correction in the LTE Downlink. J Sign Process Syst 69, 31–39 (2012). https://doi.org/10.1007/s11265-011-0643-5
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DOI: https://doi.org/10.1007/s11265-011-0643-5