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Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs

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Abstract

A scaling-friendly approach for the low-power calibration of oversampled analog-to-digital (A/D) systems is presented. A 22-dB amplifier relaxes the design constraints of the analog front-end (AFE). The integrator non-idealities in the AFE of the sigma-delta (ΣΔ) ADC are calibrated using a multi-rate polyphase least-mean squares (LMS) algorithm. The proposed half- (f s/2) and quarter-rate (f s/4) LMS calibration schemes reduce computational complexity and achieve more than 2.5× savings in digital power consumption for low-OSR (over-sampling ratio) ΔΣ ADCs, which require higher adaptive filter orders and sampling frequencies. The proposed scheme can have further applications in serial-link I/O and sub-band echo cancellation architectures.

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Authors and Affiliations

  1. Department of Electrical Engineering, Univ. of Washington, Seattle, WA, 98195, USA

    Subhanshu Gupta & David J. Allstot

  2. RFIC Engineering, Maxlinear Inc., 16275 Laguna Canyon Rd, Suite 160, Irvine, CA, 92612, USA

    Subhanshu Gupta

  3. Qualcomm Inc., San Diego, CA, 92121, USA

    Yi Tang

  4. Department of Electrical and Computer Engineering, Carnegie Mellon Univ., Pittsburgh, PA, 15213, USA

    Jeyanandh Paramesh

Authors
  1. Subhanshu Gupta
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  2. Yi Tang
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  3. Jeyanandh Paramesh
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  4. David J. Allstot
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Correspondence to Subhanshu Gupta.

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Gupta, S., Tang, Y., Paramesh, J. et al. Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs. J Sign Process Syst 69, 329–338 (2012). https://doi.org/10.1007/s11265-012-0677-3

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  • DOI: https://doi.org/10.1007/s11265-012-0677-3

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