Abstract
This paper proposes a cost-effective simplified Euclid’s (SE) algorithm for Reed-Solomon decoders, which can replace the existing modified Euclid’s (ME) algorithm. The new proposed SE algorithm, using new initial conditions and polynomials, can significantly reduce the computation complexity compared with the existing ME and reformulated inversionless Berlekamp-Massey (RiBM) algorithms, since it has the least number of coefficients in the new initial conditions. Thus, the proposed SE architecture, consisting of only 3t basic cells, has the smallest area among the existing key solver blocks, where t means the error correction capability. In addition, the SE architecture requires only the latency of 2t clock cycles to solve the key equation without initial latency. The proposed RS decoder has been synthesized using the 0.18 μm Samsung cell library, and the gate count of the RS decoder, excluding FIFO memory, is only 40,136 for the (255, 239, 8) RS code.












Similar content being viewed by others
References
Rao, T. R. N., & Fujiwara, E. (1989). Error control coding for computer systems. Englewood Cliffs: Prentice-Hall.
Wicker, S. B., & Bhargava, V. K. (1994). Reed-Solomon codes and their applications. IEEE Press.
Hsu, H. M., & Wang, C. L. (1997). An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm. IEEE Transactions on Circuits and Systems for Video Technology, 7, 864–871.
Berlekamp, E. R. (1968). Algebraic coding theory. New York: McGraw-Hill. revised – Laguna Hills, CA: Aegean Park, 1984.
Blahut, R. E. (1983). Theory and practice of error-control codes. Reading: Addison-Wesley.
Reed, I. S., & Shih, M. T. (1991). VLSI design of inverse-free Berlekamp-Massey algorithm. IEE Proceedings - Computers and Digital Techniques, 138, 295–298.
Raghupathy, A., & Liu, K. J. R. (2000). Algorithm-based low-power/high-speed Reed-Solomon decoder design. IEEE Transactions on Circuits and Systems Part II, 47, 1254–1270.
Jeng, J. H., & Truong, T. K. (1999). On decoding of both errors and erasures of a Reed-Solomon code using an inverse-free Berlekamp-Massey algorithm. IEEE Transactions on Communications, 47, 1488–1494.
Kang, H. J. & Park, I. C. (2002). A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure. in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS’ 2002), May 2002, pp. 3180–3183.
Sarwate, D. V., & Shanbhag, N. R. (2001). High-speed architectures for Reed-Solomon decoders. IEEE Transactions on Very Large Scale Integration Systems, 9, 641–655.
Shao, H. M., Truong, T. K., Deutsch, L. J., Yuen, J. H., & Reed, I. S. (1985). A VLSI design of a pipeline Reed-Solomon decoder. IEEE Transactions on Computers, C-34, 393–403.
Shao, H. M., & Reed, I. S. (1988). On VLSI design of a pipeline Reed-Solomon decoder using systolic arrays. IEEE Transactions on Computers, 37, 1273–1279.
You, Y. X., Wang, J. X., Lai, F. C., & YE, T. Z. (2002). Design and implementation of high-speed Reed-Solomon decoder. in Proc. IEEE Int. Conf. Circuits Syst. for Commun. (ICCSC), June 2002, pp. 146–149.
Song, M. K., Kim, E. B., Won, H. S., & Kong, M. H. (2002). Architecture for decoding adaptive Reed-Solomon codes with variable block length. IEEE Transactions on Consumer Electronics, 48, 631–637.
Huang, C. T., & Wu, C. W. (1996). VLSI design of a high speed pipelined Reed-Solomon CODEC. in Proc. Int. Symp. Multi-Technology Inform. Processing (ISMIP), Dec. 1996, pp. 517–522.
Lee, H. H. (2001). Modified Euclidean algorithm block for high-speed Reed-Solomon decoder. IEEE Electronics Letters, 37, 903–904.
Yuanxin, X., Fang, X., Qingdong, Y., Peiliang, Q., & Kuang, W. (2001). A new VLSI design for decoding Reed-Solomon codes based on ASIP. in Proc. Int. ASIC Conference, pp. 448–451.
Hsu, H. Y., Yeo, J. C., & Wu, A. Y. (2006). Multi-symbol-sliced dynamically reconfigurable Reed-Solomon decoder design based on unified finite-field processing element. IEEE Transactions on Very Large Scale Integration Systems, 14, 489–500.
Baek, J. H., & Sunwoo, M. H. (2006). New degree computationless modified Euclid’s algorithm and architecture for Reed-Solomon decoder. IEEE Transactions on Very Large Scale Integration, 14, 915–920.
Lee, S. B., Lee, H. H., Shin, J. Y., & Ko, J. S. (2007). A high-speed pipelined degree-computationless modified euclidean algorithm architecture for Reed-Solomon decoders. in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS’ 2007), May 2007, pp. 901–904.
Baek, J. H., & Sunwoo, M. H. (2007). Simplified degree computationless modified Euclid’s algorithm and its architecture. in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS’ 2007), May 2007, pp. 905–908.
Acknowledgments
This work was supported under the framework of international cooperation program managed by National Research Foundation of Korea (2011-0030930) and Mid-career Researcher Program through the NRF grant funded by the MEST (20120005313).
Author information
Authors and Affiliations
Consortia
Corresponding author
Rights and permissions
About this article
Cite this article
Baek, J., Sunwoo, M.H. & Fellow Member IEEE. New Cost-Effective Simplified Euclid’s Algorithm for Reed-Solomon Decoders. J Sign Process Syst 71, 159–168 (2013). https://doi.org/10.1007/s11265-012-0692-4
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-012-0692-4