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Hierarchical Resampling Algorithm and Architecture for Distributed Particle Filters

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Abstract

In this paper, we introduce a hierarchical resampling (HR) algorithm and architecture for distributed particle filters (PFs). While maintaining the same accuracy as centralized resampling in statistics, the proposed HR algorithm decomposes the resampling step into two hierarchies including intermediate resampling (IR) and unitary resampling (UR), which suits PFs for distributed hardware implementation. Also presented includes a residual cumulative resampling (RCR) method that pipelines and accelerates the UR step. The corresponding architecture, when compared with traditional distributed architectures, eliminates the particle redistribution step, and has such advantages as short execution time and high memory efficiency. The prototype containing 8 PEs has been developed in Xilinx Virtex IV FPGA (XC4VFX100-12FF1152) for the bearings-only tracking (BOT) problem, and the result shows that the input observations can be processed at 37.21 KHz with 8 K particles and a clock speed of 80 MHz.

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Acknowledgments

The authors would like to thank Zhuoran Zhao and Ye Wang for their contributions in the hardware implementation.

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Correspondence to Yun Pan.

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This research was supported by Zhejiang Provincial Natural Science Foundation of China (No. LQ12F04002) and the National Natural Science Foundation of China (No. 61204030). Part of the work in this paper was presented at the 2012 IEEE International Conference on Acoustics, Speech and Signal Processing.

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Pan, Y., Zheng, N., Tian, Q. et al. Hierarchical Resampling Algorithm and Architecture for Distributed Particle Filters. J Sign Process Syst 71, 237–246 (2013). https://doi.org/10.1007/s11265-012-0712-4

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  • DOI: https://doi.org/10.1007/s11265-012-0712-4

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