Abstract
With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.
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Acknowledgment
The authors would like to thank the IC Design Education Center (IDEC) for its software assistance.
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This work is supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2010-0004484).
Appendix A
Appendix A
The \(MSE_{\mathrm {err}}\) in Eq. (13) is derived as follows: In the one luma pixel, the numerical value of the pixel data (Y) and the memory bit-cell failures (F) are expressed as: \(Y=\sum\limits _{i=0}^{7} y_{i} \cdot 2^{i}\) And \(F=\sum\limits _{i=0}^{7} f_{i} \cdot 2^{i}\), respectively.
Using the expected error values due to the memory failures, the \(MSE_{\mathrm {err}}\) can be expressed as:
where \(C_{i}\) is the distortion ratio of the \(i_{th}\) order of memory bit-cell failures.
Considering the fact that the memory bit-cell failures are independent to each other and the probabilities of the flip directions \((p_{0\rightarrow 1} = p_{1\rightarrow 0} = \frac {1}{2})\)are generally the same, we can change the above equation to:
Assuming that each bit in the luma pixel data are independent each other, the second term of the above equation can be written as:
where
\(p_{i}\) is the failure probability of a memory bit-cell. Therefore, \(MSE_{\mathrm {err}}\) is expressed as:
When the PB-ECC is used, the \(p_{i}\) of the HPP and LPP are equal to \(P_{b_{HPP}} (E,k_{HPP})\) and \(P_{b_{LPP}} (E,k_{LPP})\), respectively. \(MSE_{\mathrm {err}}\) is divided into two parts as:
where, h is the number of bit allocation. \(\alpha (h)\) and \(\beta (h)\) are the sum of the expected numerical square value of the errors in HPP and LPP, respectively.
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Lee, I., Kwon, J., Park, J. et al. Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System. J Sign Process Syst 73, 123–136 (2013). https://doi.org/10.1007/s11265-013-0736-4
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DOI: https://doi.org/10.1007/s11265-013-0736-4