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Optimizing Data Placement of Loops for Energy Minimization with Multiple Types of Memories

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Abstract

Strict real-time processing and energy efficiency are required by high-performance Digital Signal Processing (DSP) applications. Scratch-Pad Memory (SPM), a software-controlled on-chip memory with small area and low energy consumption, has been widely used in many DSP systems. Various data placement algorithms are proposed to effectively manage data on SPMs. However, none of them can provide optimal solution of data placement problem for array data in loops. In this paper, we study the problem of how to optimally place array data in loops to multiple types of memory units such that the energy and time costs of memory accesses can be minimized. We design a dynamic programming algorithm, Iterational Optimal Data Placement (IODP), to solve data placement problem for loops for processor architectures with multiple types of memory units. According to the experimental results, the IODP algorithm reduced the energy consumption by 20.04 % and 8.98 % compared with a random memory placement method and a greedy algorithm, respectively. It also reduced the memory access time by 19.01 % and 8.62 % compared with a random memory placement method and a greedy approach.

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References

  1. Cacti model. http://www.hpl.hp.com/research/cacti/.

  2. Absar, M., & Catthoor, F. (2005). Compiler-based approach for exploiting scratch-pad in presence of irregular array access. In Design, automation and test in Europe, 2005. Proceedings (pp. 1162–1167). IEEE.

  3. Avissar, O., Barua, R., Stewart, D. (2002). An optimal memory allocation scheme for scratch-pad-based embedded systems. ACM Transactions on Embedded Computing Systems (TECS), 1(1), 6–26.

    Article  Google Scholar 

  4. Banakar, R., Steinke, S., Lee, B., Balakrishnan, M., Marwedel, P. (2002). Scratchpad memory: design alternative for cache on-chip memory in embedded systems. In Proceedings of the tenth international symposium on hardware/software codesign (pp. 73–78). ACM.

  5. Chen, G., Ozturk, O., Kandemir, M., Karakoy, M. (2006). Dynamic scratch-pad memory management for irregular array access patterns. In Proceedings of the conference on design, automation and test in Europe: proceedings (pp. 931–936). European Design and Automation Association.

  6. Chen, Z., Qiu, M., Niu, J., Lu, Z., Zhu, Y. (2012). Data allocation using genetic algorithm for MPSoc systems with hybrid scratch-pad memory. In Proceedings of the 18th IEEE real time and embedded technology and applications symposium(RTAS) (pp. 61–64).

  7. Dominguez, A., Udayakumaran, S., Barua, R. (2005). Heap data allocation to scratch-pad memory in embedded systems. Journal of Embedded Computing, 1(4), 521–540.

    Google Scholar 

  8. Hu, J., Xue, C., Tseng, W., He, Y., Qiu, M., Sha, E. (2010). Reducing write activities on non-volatile memories in embedded cmps via data migration and recomputation. In Design automation conference (DAC), 2010 47th ACM/IEEE (pp. 350–355). IEEE.

  9. Hu, J., Xue, C., Tseng, W., Zhuge, Q., Sha, E. (2010). Minimizing write activities to non-volatile memory via scheduling and recomputation. In Application specific processors (SASP), 2010 IEEE 8th symposium on (pp. 101–106). IEEE.

  10. Hu, J., Xue, C., Zhuge, Q., Tseng, W., Sha, E. (2011). Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory. In Design, automation & test in europe conference & exhibition (DATE) (pp. 1–6). IEEE.

  11. Ozturk, O., Kandemir, M., Kolcu, I. (2006). Shared scratch-pad memory space management. In Quality electronic design, 2006. ISQED’06. 7th international symposium on (pp. 6–12). IEEE.

  12. Ozturk, O., Kandemir, M., Narayanan, S. (2008). A scratch-pad memory aware dynamic loop scheduling algorithm. In Quality electronic design, 2008. ISQED 2008. 9th international symposium on (pp. 738–743). IEEE.

  13. Panda, P., Dutt, N., Nicolau, A. (1997). Efficient utilization of scratch-pad memory in embedded processor applications. In Proceedings of the 1997 European conference on design and test (p. 7). IEEE Computer Society.

  14. Panda, P., Dutt, N., Nicolau, A. (2000). On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), 5(3), 682–704.

    Article  Google Scholar 

  15. Qiu, M., & Sha, E.H.M. (2009). Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), 14(2), 1–30.

    Article  Google Scholar 

  16. Sjödin, J., & Von Platen, C. (2001). Storage allocation for embedded processors. In Proceedings of the 2001 international conference on compilers, architecture, and synthesis for embedded systems (pp. 15–23). ACM.

  17. Tseng, W., Xue, C., Zhuge, Q., Hu, J., Sha, E. (2010). Optimal scheduling to minimize non-volatile memory access time with hardware cache. In VLSI system on chip conference (VLSI-SoC), 2010 18th IEEE/IFIP (pp. 131–136). IEEE.

  18. Udayakumaran, S., & Barua, R. (2003). Compiler-decided dynamic memory allocation for scratch-pad based embedded systems. In Proceedings of the 2003 international conference on compilers, architecture and synthesis for embedded systems (pp. 276–286). ACM.

  19. Udayakumaran, S., Dominguez, A., Barua, R. (2006). Dynamic allocation for scratch-pad memory using compile-time decisions. ACM Transactions on Embedded Computing Systems (TECS) , 5(2), 472–511.

    Article  Google Scholar 

  20. Zhuge, Q., Guo, Y., Hu, J., Tseng, W., Xue, S., Sha, E. (2012). Minimizing access cost for multiple types of memory units in embedded systems through data allocation and scheduling. Signal Processing, IEEE Transactions on, 60(6), 3253–3263.

    Article  MathSciNet  Google Scholar 

  21. Zivojnovic, V., Velarde, J., Schlager, C., Meyr, H. (1994). Dspstone: a dsp-oriented benchmarking methodology. In Proceedings of the international conference on signal processing and technology.

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Acknowledgments

This work is partially supported by NSF CNS-1015802, Texas NHARP 009741-0020-2009, NSFC 61173014, National 863 Program 2013AA013202, Chongqing cstc2012ggC40005.

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Correspondence to Qingfeng Zhuge.

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Zhang, J., Deng, T., Gao, Q. et al. Optimizing Data Placement of Loops for Energy Minimization with Multiple Types of Memories. J Sign Process Syst 72, 151–164 (2013). https://doi.org/10.1007/s11265-013-0774-y

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  • DOI: https://doi.org/10.1007/s11265-013-0774-y

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