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Fast Algorithm and Efficient Architecture for Integer and Fractional Motion Estimation

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Abstract

Motion estimation in H.264/AVC, is done in two parts – integer motion estimation, and fractional motion estimation. Hardware reuse for both parts is inefficient due to the differences between them. In this paper we address the hardware reuse problem by proposing a, fast motion estimation algorithm as well as a pipelined FPGA-based, field programmable system-on-chip (FPSoC), for integer and fractional motion estimation. Our results show that the rate-distortion loss of our algorithm is insignificant when compared to full search in H.264/AVC. Its average Y-PSNR loss is 0.065 dB, its average percentage bit rate increase is 5 %, and its power consumption is 76 mW. Our FPSoC is hardware-efficient, even out-performing some state-of-the-art ASIC implementations. It can support up to high definition 1280 × 720p video at 24Hz. Thus, our proposed algorithm and architecture is suitable for delivery of high quality video on low power devices and low bit rate applications which typically use H.264/AVC baseline profile@levels 1–3.1.

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Authors and Affiliations

  1. Santa Clara University, Santa Clara, CA, USA

    Obianuju Ndili & Tokunbo Ogunfunmi

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  1. Obianuju Ndili
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  2. Tokunbo Ogunfunmi
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Correspondence to Tokunbo Ogunfunmi.

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Ndili, O., Ogunfunmi, T. Fast Algorithm and Efficient Architecture for Integer and Fractional Motion Estimation. J Sign Process Syst 75, 55–64 (2014). https://doi.org/10.1007/s11265-013-0793-8

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  • DOI: https://doi.org/10.1007/s11265-013-0793-8

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