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Symbolic Mapping of Loop Programs onto Processor Arrays

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Abstract

In this paper, we present a solution to the problem of joint tiling and scheduling a given loop nest with uniform data dependencies symbolically. This challenge arises when the size and number of available processors for parallel loop execution is not known at compile time. But still, in order to avoid any overhead of dynamic (run-time) recompilation, a schedule of loop iterations shall be computed and optimized statically. In this paper, it will be shown that it is possible to derive parameterized latency-optimal schedules statically by proposing a two step approach: First, the iteration space of a loop program is tiled symbolically into orthotopes of parametrized extensions. Subsequently, the resulting tiled program is also scheduled symbolically, resulting in a set of latency-optimal parameterized schedule candidates. At run time, once the size of the processor array becomes known, simple comparisons of latency-determining expressions finally steer which of these schedules will be dynamically selected and the corresponding program configuration executed on the resulting processor array so to avoid any further run-time optimization or expensive recompilation. Our theory of symbolic loop parallelization is applied to a number of loop programs from the domains of signal processing and linear algebra. Finally, as a proof of concept, we demonstrate our proposed methodology for a massively parallel processor array architecture called tightly coupled processor array (TCPA) on which applications may dynamically claim regions of processors in the context of invasive computing.

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Notes

  1. Following the well-known LSGP (locally sequential, globally parallel) static mapping principle.

  2. In the following, we assume w.l.o.g. that we start from a UDA, as any linear dependence algorithm may be systematically transformed into a UDA using localization, see, e. g., [42, 43].

  3. In the following, we do not necessarily require to assume perfect tilings, as due to Eq. 2, each variable may be defined over an individual subspace of the global loop iteration space \(\mathcal {I}\). Moreover, we may assume in the following w.l.o.g. that \(\mathcal {I}\) is the rectangular hull of the union of all the \(\mathcal {I}_i\) in Eq. 2.

  4. We assume for simplicity that a single iteration of a given loop may be executed in a unit of time.

  5. We assume for regularity of a schedule that each tile is scheduled equally in exactly det(P) time steps, even if the covering of the union of the iteration spaces of all G equations of a given UDA might lead to some non-perfectly filled tiles.

  6. Loops with affine data dependencies [39, 40] or certain classes of dynamic data dependencies [14] may converted first in this form, e.g., by localization of data dependencies [43] or hiding data-value dependent computations by data-dependent functions [10, 14].

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Acknowledgments

This work was supported by the German Research Foundation (DFG) as part of the Transregional Collaborative Research Centre “Invasive Computing” (CRC 89).

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  1. University of Erlangen-Nüremberg (FAU), Cauerstr. 11, 91058, Erlangen, Germany

    Jürgen Teich, Alexandru Tanase & Frank Hannig

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Teich, J., Tanase, A. & Hannig, F. Symbolic Mapping of Loop Programs onto Processor Arrays. J Sign Process Syst 77, 31–59 (2014). https://doi.org/10.1007/s11265-014-0905-0

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