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Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware

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Abstract

Designing hardware often involves several types of modeling and analysis, e.g., in order to check system correctness, to derive performance properties such as throughput, to optimize resource usages (e.g., buffer sizes), and to synthesize parts of a circuit (e.g., control logic). Working directly with low-level hardware models such as finite-state machines (FSMs) to answer such questions is often infeasible, e.g., due to state explosion. Instead, designers often use dataflow models such as SDF and CSDF, which are more abstract than FSMs, and less expensive to use since they come with more efficient analysis algorithms. However, dataflow models are only abstractions of the real hardware, and often omit critical information. This raises the question, when can one say that a certain dataflow model faithfully captures a given piece of hardware? The question is of more than simply academic interest. Indeed, as illustrated in this paper, dataflow-based analysis outcomes may sometimes be defensive (e.g., buffers that are too big) or even incorrect (e.g., buffers that are too small). To answer the question of faithfully capturing hardware using dataflow models, we develop a formal conformance relation between the heterogeneous formalisms of (1) finite-state machines with synchronous semantics, typically used to model synchronous hardware, and (2) asynchronous processes communicating via queues, used as a formal model for dataflow. The conformance relation preserves performance properties such as worst-case throughput and latency.

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Notes

  1. Our formal dataflow model is similar to standard timed dataflow models such as timed SDF [7]. Original works on dataflow models such as SDF consider their untimed versions, e.g., [3, 8]. Timed properties such as throughput cannot be evaluated on untimed models. For this reason, we work with timed dataflow models.

  2. For simplicity, we use deterministic FSMs. However, the results, and in particular the definition of conformance, directly extend to non-deterministic FSMs as well.

  3. For simplicity, in our examples we assume no auto-concurrency, that is, no overlapping of firings of the same process. Auto-concurrency can be captured in our model using more elaborate and potentially infinite-state processes.

  4. Examples of CSDF processes can be found in Fig. 21.

  5. An alternative could be to attempt to discover consumptions and productions automatically by observing the behavior of the FSM. This problem is much more difficult, and is the topic of future work.

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Acknowledgments

This work was partially supported by the Academy of Finland and by the NSF via projects COSMOI: Compositional System Modeling with Interfaces and ExCAPE: Expeditions in Computer Augmented Program Engineering. This work was also partially supported by IBM and United Technologies Corporation (UTC) via the iCyPhy consortium, and by Denso, National Instruments, and Toyota, via the UC Berkeley Center for Hybrid and Embedded Software Systems (CHESS).

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Authors and Affiliations

  1. University of California, Berkeley, CA, USA

    Stavros Tripakis

  2. Aalto University, Espoo, Finland

    Stavros Tripakis

  3. National Instruments Corporation, Berkeley, CA, USA

    Rhishikesh Limaye, Kaushik Ravindran, Guoqiang Wang, Hugo Andrade & Arkadeb Ghosal

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  1. Stavros Tripakis
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  2. Rhishikesh Limaye
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  6. Arkadeb Ghosal
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Correspondence to Stavros Tripakis.

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Tripakis, S., Limaye, R., Ravindran, K. et al. Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware. J Sign Process Syst 85, 23–43 (2016). https://doi.org/10.1007/s11265-015-0971-y

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