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A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

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Abstract

In the past years, many works have demonstrated the applicability of Coarse-Grained Reconfigurable Array (CGRA) accelerators to optimize loops by using software pipelining approaches. They are proven to be effective in reducing the total execution time of multimedia and signal processing applications. However, the run-time reconfigurability of CGRAs is hampered overheads introduced by the needed translation and mapping steps. In this work, we present a novel run-time translation technique for the modulo scheduling approach that can convert binary code on-the-fly to run on a CGRA. We propose a greedy approach, since the modulo scheduling for CGRA is an NP-complete problem. In addition to read-after-write dependencies, the dynamic modulo scheduling faces new challenges, such as register insertion to solve recurrence dependences and to balance the pipelining paths. Our results demonstrate that the greedy run-time algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for a 16-issue VLIW processor. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated. In this analysis it is demonstrated that when changing from one memory access per cycle to two memory accesses per cycle, the modulo scheduling algorithm is able to exploit this increase in memory bandwidth and enhance performance accordingly. Additionally, to measure area and performance, the proposed CGRA was prototyped on an FPGA. The area comparisons show that a crossbar CGRA (with 16 processing elements and including an 4-issue VLIW host processor) is only 1.11 × bigger than a standalone 8-issue VLIW softcore processor.

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Authors and Affiliations

  1. Universidade Federal de Viçosa, Vicosa, Minas Gerais, Brazil

    Ricardo Ferreira & Waldir Denver

  2. Universidade Federal do Rio Grande do Norte, Natal, Rio Grande do Norte, Brazil

    Monica Pereira

  3. TU Delft, Delft, Netherlands

    Stephan Wong

  4. Universidade Federal do Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil

    Carlos A. Lisbȏa & Luigi Carro

Authors
  1. Ricardo Ferreira
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  2. Waldir Denver
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  3. Monica Pereira
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  4. Stephan Wong
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  5. Carlos A. Lisbȏa
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  6. Luigi Carro
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Correspondence to Ricardo Ferreira.

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Ferreira, R., Denver, W., Pereira, M. et al. A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility. J Sign Process Syst 85, 45–66 (2016). https://doi.org/10.1007/s11265-015-0974-8

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  • DOI: https://doi.org/10.1007/s11265-015-0974-8

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