Abstract
Constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units and they are prevalent in modern VLSI designs. This study presents efficient algorithms and their fast hardware implementation for performing multiplying-by-(2k ± 1), or (2k ± 1)N, operation with additions. No multiplications are needed. The value of (2k ± 1)N can be computed by adding (±N) to its k-bits left-shifted value 2kN. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper presents the unit cells for additions (UCAs). Results show that the UCA-based RCA achieves 34 % faster than the FA-based RCA. Further, in order to improve the speed performance with lower hardware cost, this paper also presents a simple and modular hybrid adder with the proposed UCA concept, where the hybrid adder takes the lower-bit carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the proposed hybrid adder achieved speed performance improvement while maintaining its modular and regular structure.
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Cappello, P. R., & Steiglitz, K. (1984). Some complexity issues in digital signal processing. IEEE Transactions on Acoustics, Speech, and Signal Processing, 32(No. 5), 1037–1041.
Wey, C. L., Jui, P.-C., & Sung, G.-N. (2014). Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97-A(2), 616–623.
Jui, P.-C., Sung, G.-N., & Wey, C. L. (2012). Efficient algorithm and hardware implementation of 3N for arithmetic and for radix-8 encodings, Proc. of IEEE Midwest Symp. on Circuits and Systems, Boise, Idaho (pp. 418–421).
Oudjida, A. K., & Chaillet, N. (2014). Radix-2r Arithmetic for multiplication by a constant. IEEE Transactions on Circuits and Systems – II: Express Briefs, 61, 349–353.
Koren, I. (1993). Computer arithmetic algorithms. New Jersey: Prentice-Hall, Inc.
Huang, K. (1979). Computer arithmetic: principles, architecture, and design. New York: Wiley.
Chang, S.-K., & Wey, C. L. (2012). A fast 64-bit hybrid adder design in 90 nm CMOS process. Boise: Proc. of IEEE Midwest Symp. on Circuits and Systems.
Brent, R. P., & Kung, H. T. (1982). A regular layout for parallel adders. IEEE Transactions on Computers, 31(3), 260–264.
Wey, C. L. (1996). Built-In Self-Test (BIST) design of high-speed carry-free dividers. IEEE Transactions on VLSI Systems, 4(1), 141–145.
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Jui, PC., Wey, CL. & Shiue, MT. Multiplication of a Constant (2k ± 1) and Its Fast Hardware Implementation. J Sign Process Syst 82, 41–53 (2016). https://doi.org/10.1007/s11265-015-0978-4
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DOI: https://doi.org/10.1007/s11265-015-0978-4